Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis

<div>CLK period (ns) for <svg height="9.04777pt" id="M91" style="vertical-align:-0.04981995pt" version="1.1" viewbox="-0.0498162 -8.99795 9.65971 9.04777" width="9.65971pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.0135,0,0,-0.0135,0,0)"><path d="M686 28C612 35 607 44 591 112C563 234 541 360 519 489L489 666L457 658L147 121C100 40 89 36 24 28L17 0H240L250 28C168 34 159 41 190 101L262 237H482C495 180 503 137 510 91C517 47 514 35 441 28L433 0H677L686 28ZM475 280H285L429 541H431L475 280Z" id="g113-66"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="703" vert-adv-y="703"></glyph.data></g></svg>[7:0] × 8-bit constant.</div>

International Journal of Reconfigurable Computing

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Figure 8

Figure 8: Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis 