Research Article
AC_ICAP: A Flexible High Speed ICAP Controller
Table 2
Timing behavior of AC_ICAP.
| ā | Controller | LUT Reconf. [s] | ReadFrame [s] | WriteFrame [s] | Reconf. throughput from BRAM [MB/s] | Reconf. throughput from flash [MB/s] |
| Kintex7 | AC_ICAP | 10.91 | 2.39 | 2.33 | 380.47 | 14.66 | AXI_AC_ICAP | 11.78 | 3.06 | 3.01 | 378.37 | 14.65 | AXI_HWICAP [19] | n/a | 58.08 | 63.54 | n/a | 1.25 |
| Virtex-5 | AC_ICAP | 4.98 | 1.18 | 1.17 | 381.03 | 14.67 | PLB_AC_ICAP | 5.88 | 1.90 | 1.90 | 378.73 | 14.66 | FSL_AC_ICAP | 5.36 | 1.57 | 1.56 | 378.85 | 14.67 | XPS_HWICAP [4] | 1912.17 | 29.21 | 32.16 | n/a | 1.32 | [15] | n/a | n/a | n/a | 384.29 | 6.57 | [14] | n/a | n/a | n/a | n/a | 0.86 |
| Virtex-4 | [20] | n/a | n/a | n/a | 371.42 | n/a | BRAM_HWICAP [11] | n/a | n/a | n/a | 371.4 | n/a | ICAP-I [16] | n/a | n/a | n/a | 180 | 29 |
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All 7-series FPGAs are 6-input LUTs, frames of 101 32-bit words. Virtex-5: 6-input LUTs, frames of 41 32-bit words. Valid for SD memory AT49BV322A. Virtex4: 4-input LUTs, frames of 41 32-bit words. Estimated value, not implemented.
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