An Improved Diffusion Based Placement Algorithm for Reducing Interconnect Demand in Congested Regions of FPGAs

Table 1

Results produced by VPR for cluster size .

Netlist	FPGA size	VPR			Diffusion based placement
		Wirelength		Channel width	Wirelength		Channel width
alu4	40 × 40	21826	5.72	10	23269	5.44	10
apex2	44 × 44	33355	5.8	12	35428	5.75	12
apex4	36 × 36	24052	7.56	14	25166	6.78	12
bigkey	42 × 42	20502	3.55	8	20939	3.54	8
des	40 × 40	25365	3.78	10	26137	3.48	10
diffeq	39 × 39	18204	3.82	8	19830	3.61	8
dsip	38 × 38	16891	3.53	8	19830	3.61	8
ex5p	33 × 33	22717	8.9	14	24040	8.83	14
misex3	38 × 38	23585	6.67	12	24534	5.08	10
seq	42 × 42	31026	6.6	12	32226	5.71	12
tseng	33 × 33	12773	3.61	8	14093	3.46	8
s298	44 × 44	16728	3.49	8	17425	3.18	8
elliptic	61 × 61	47603	7	10	52001	4.71	10
frisc	60 × 60	59959	7.14	12	62569	5.78	12
spla	61 × 61	67065	7.72	14	72017	6.57	14
s38417	81 × 81	83355	4.3	8	86291	4.22	8
ex1010	68 × 68	78798	4.88	12	81029	4.62	12
Pdc	68 × 68	98470	9.86	16	104287	7.84	16
s38584.1	81 × 81	79180	4.5	8	87642	3.99	8
clma	92 × 92	140105	6.06	12	151582	5.01	12