Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs

Table 2

Parameter values for selected core instances in case studies.

Parameters	Mult						Add						FLT_FIXED						FIXED_FLT
	Xilinx			Altera			Xilinx			Altera			Xilinx			Altera			Xilinx			Altera
Frequency; (MHz)	397	429	504	400	431	605	378	450	652	375	499	714	354	503	498	240	410	639	482	550	600	445	462	653
DSP usage	4	2	2	4	4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
FF usage	254	183	36	1125	391	293	588	557	221	902	678	902	289	256	66	379	361	379	227	201	224	345	371	345
Latency (cycles)	10	8	8	11	11	11	13	12	12	14	14	14	6	6	6	6	6	6	7	7	7	6	6	6

First column of Xilinx is for Virtex-4 LX100, second is for Virtex-6 LX130, and third is for Virtex-7 VX330T.
First column of Altera is for Stratix-II S180, second is for Stratix-IV S40, and third is for Stratix-V GSD3.