Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs

Table 4

Core-level DSE example for SPFP FIR filters (MHz).

(a) 8-tap SPFP FIR filter on Xilinx Virtex-4 LX100

For all mult	For all adder	Verified	Predicted
			CMD	LCF	ALCF	Postsynthesis
Full, 4 DSPs	No, 0 DSPs	319	317	378	284	188
Max, 5 DSPs	No, 0 DSPs	254	257	378	284	188
Max, 5 DSPs	Full, 4 DSPs	215	219	390	293	188
No, 0 DSPs	Full, 4 DSPs	268	261	280	210	184
Medium, 1 DSP	Full, 4 DSPs	280	279	300	225	188
Full, 4 DSPs	Full, 4 DSPs	333	326	390	293	188
No, 0 DSPs	No, 0 DSPs	271	262	280	210	184
Medium, 1 DSP	No, 0 DSPs	278	279	300	225	188

(b) 48-tap SPFP FIR filter on Xilinx Virtex-4 LX100

For all mult	For all adder	Verified	Predicted
			CMD	LCF	ALCF	Postsynthesis
Medium, 1 DSP	No, 0 DSPs	249	244	300	225	188
No, 0 DSPs	No, 0 DSPs	271	262	280	210	188

(c) 96-tap SPFP FIR filter on Altera Stratix-II S180

For all mult	For all adder	Verified	Predicted
			CMD	LCF	ALCF
4 DSPs	0 DSPs	202	205	350	263
0 DSPs	0 DSPs	214	214	251	188