Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs

Table 5

Example of productivity gains from using CMD for 8-tap FIR filter.

	(a) 30-node cluster		(b) Single node
Breakdown of dev. time	1	2	1	2
Formulation w/ CMD	N/A	1 hr	N/A	1 hr
Write impl. HDL code	8 hrs	6 hrs	8 hrs	6 hrs
Binary freq. search	40 hrs	N/A	40 hrs	3 hrs
Exhaustive freq. search	8 hrs	1 hr	N/A	N/A
Total design time	56 hrs	8 hrs	48 hrs	10 hrs
Result frequency	333 MHz	333 MHz	310 MHz	310 MHz

Column 1: traditional design method (no CMD or binary/exhaustive frequency-search methods).
Column 2: core-level DSE, code-template/constraints generation, and frequency-search tools.