Comment on “High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs”

Figure 1

Mapping of (1,4,1,5;5) GPC to Xilinx Virtex 5.

(a) GPC from [1], claimed to use two LUTs

(b) Slice mapping of previous GPC [2] using four LUTs

(c) Corrected Slice mapping of GPC from [1] requiring four LUTs