| // import SdrHls DSL compiler |
| import sdrg.dsl.sdrhls._ |
| import sdrg.dsl.sdrhls.dsp.fir.Compensator |
| // include lms, delite libraries |
| object SdrHlsMainRunner extends SdrHlsApplicationRunner with SdrHlsMain |
| trait SdrHlsMain extends SdrHlsApplication |
| def main() |
| // generate a list of compensating filter coefficients |
| val filter = Compensator(128, 10, 1) |
| // set generic parameters for DDC |
| valddcParams = ("DIN_WIDTH" -> 16, "DOUT_WIDTH" -> 16, |
| "COEFFS" -> filter.coefficients, |
| // other parameters |
| ... |
| ) |
| // set generic parameters for Gigabit Ethernet |
| valgbeParams = ("TX_BYTES", 64) |
| // define FM receiver components |
| valadc = Component("fmc150", Nil) |
| valddc = Component("DDC", ddcParams) |
| valgbe = Component("UDP1GbE", gbeParams) |
| // the chain of system components |
| val radio = Chain(adc[0:1], ddc[1:1], gbe[16:0]) |
| // generate VHDL code for the FM Receiver |
| radio.synthesize("FmReceiver") |
|
| |
