A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

Algorithm 2

Force-Directed Scheduling.

Input: Dataflow graph representation of the design

Output: Operator assignments to cycles

while  there are unscheduled operations  do

Step 1. Evaluate time frames;

Step 2. Update distribution graphs;

Step 3. Calculate self-forces for every feasible cycle;

Step 4. Calculate total force from self-force, predecessor force, and successor force;

Step 5. Schedule operation with lowest force;

end