Research Article

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

Table 1

Benchmark summary.

Benchmark DescriptionNumber of nodesNumber of edgesOperation types

conv5x55x5 convolution kernel.49190Add, Mult
conv9x99x9 convolution kernel.161932Add, Mult
fft88-point radix-2 DIT FFT based on butterfly architecture.32116Add, Sub, Mult
fft1616-point radix-2 DIT FFT based on butterfly architecture.88648Add, Sub, Mult
fftrad44-point radix-4 FFT based on dragonfly architecture. Efficiently decomposing complex operations into real operations.40232Add, Sub, Mult
linsorSingle iteration kernel to solve a system of linear equations () in 5 variables, using successive-overrelaxation (SOR) method.642657Add, Sub, Mult, Div
linjacobiSingle iteration kernel to solve a system of linear equations in 5 variables, using Jacobi method.60230Add, Sub, Mult, Div
lapsorSingle iteration kernel to solve Laplace’s equation (), using successive-overrelaxation (SOR) method.716Add, Sub, Mult
lapjacobiSingle iteration kernel to solve Laplace’s equation using Jacobi method.59Add, Sub, Mult
small0–78 randomly generated DFGs with 20 operations.4–192–36Add, Mult
medium0–45 randomly generated DFGs with 130 operations.88–127346–642Add, Sub, Mult, Div