Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

<div>Number of CLBs utilized for cluster size of <svg height="8.8423pt" id="M93" style="vertical-align:-0.2064009pt" version="1.1" viewbox="-0.0498162 -8.6359 38.4976 8.8423" width="38.4976pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M822 650H589L583 622C660 617 677 607 674 561C672 534 664 481 647 390L600 137H596L273 650H126L120 622C176 620 194 615 207 594C221 571 225 557 214 504L161 257C141 166 129 112 121 85C108 42 83 30 29 28L23 0H260L266 28C193 33 173 42 176 89C178 122 186 172 202 255L256 527H259L583 -8H612L690 390C708 481 720 535 728 558C744 603 756 619 816 622L822 650Z" id="g113-79"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="839" vert-adv-y="839" xpluscharwidth="10.907"></glyph.data></g><g transform="matrix(.013,0,0,-0.013,14.542,0)"><path d="M535 323V373H52V323H535ZM535 138V188H52V138H535Z" id="g117-34"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="587" vert-adv-y="587" xpluscharwidth="22.173000000000002"></glyph.data></g><g transform="matrix(.013,0,0,-0.013,25.805,0)"><path d="M384 0V27C293 34 287 42 287 114V635C232 613 172 594 109 583V559L157 557C201 555 205 550 205 499V114C205 42 199 34 109 27V0H384Z" id="g113-50"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="480" vert-adv-y="480" xpluscharwidth="32.045"></glyph.data></g><g transform="matrix(.013,0,0,-0.013,32.045,0)"><path d="M137 343C167 482 260 545 321 574C357 591 397 603 429 609L423 641C382 634 335 622 295 608C189 570 37 457 37 238C37 84 125 -12 242 -12C362 -12 447 89 447 209C447 311 374 393 267 393C247 393 226 386 204 376L137 343ZM227 337C318 337 361 256 361 173C361 105 336 22 258 22C176 22 126 120 126 240C126 266 127 291 132 310C155 323 189 337 227 337Z" id="g113-55"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="480" vert-adv-y="480" xpluscharwidth="38.285000000000004"></glyph.data></g></svg> and <svg height="10.2124pt" id="M94" style="vertical-align:-3.42943pt" version="1.1" viewbox="-0.0498162 -6.78297 7.83752 10.2124" width="7.83752pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M570 304C570 398 525 448 414 448C385 448 343 445 312 434L329 511L321 518C297 504 262 482 244 460L233 411C195 397 159 381 128 358L135 332C160 347 189 360 224 373L111 -147C97 -210 84 -218 17 -231L13 -257L254 -247L259 -218L233 -216C183 -212 177 -202 189 -142L218 -1C238 -10 266 -12 283 -12C351 3 429 48 483 105C543 168 570 242 570 304ZM482 289C482 161 380 33 304 33C278 33 248 51 233 69L303 396C326 400 352 403 369 403C428 403 482 380 482 289Z" id="g113-113"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="593" vert-adv-y="593" xpluscharwidth="7.709"></glyph.data></g></svg> = 1–8.</div>

International Journal of Reconfigurable Computing

fig8

Figure 8

Figure 8: Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing 