Abstract
Reconfigurable logic devices (RLDs) are classified as the
fine-grained or coarse-grained type based on their basic logic
cell architecture. In general, each architecture has its own
advantage. Therefore, it is difficult to achieve a balance between
the operation speed and implementation area in various
applications. In the present paper, we propose a variable
grain logic cell (VGLC) architecture, which consists of a 4-bit ripple carry adder with configuration
memory bits and
develop a technology mapping tool. The key feature of the
VGLC architecture is that the variable granularity is a tradeoff
between coarse-grained and fine-grained types required
for the implementation arithmetic and random logic, respectively.
Finally, we evaluate the proposed logic cell using the
newly developed technology mapping tool, which improves
logic depth by 31% and reduces the number of configuration
data by 55% on average, as compared to the Virtex-4 logic
cell architecture.