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Citations to this Journal [278 citations: 1–100 of 251 articles]

Articles published in International Journal of Reconfigurable Computing have been cited 278 times. The following is a list of the 251 articles that have cited the articles published in International Journal of Reconfigurable Computing.

  • Bernd Bischl, Pascal Kerschke, Lars Kotthoff, Marius Lindauer, Yuri Malitsky, Alexandre Fréchette, Holger Hoos, Frank Hutter, Kevin Leyton-Brown, Kevin Tierney, and Joaquin Vanschoren, “ASlib: A benchmark library for algorithm selection,” Artificial Intelligence, vol. 237, pp. 41–58, 2016. View at Publisher · View at Google Scholar
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  • Abdelkarim Cherkaoui, Lilian Bossuet, and Cedric Marchand, “Design, Evaluation, and Optimization of Physical Unclonable Functions Based on Transient Effect Ring Oscillators,” IEEE Transactions on Information Forensics and Security, vol. 11, no. 6, pp. 1291–1305, 2016. View at Publisher · View at Google Scholar
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  • Jihyuck Jo, Hoyoung Yoo, and In-Cheol Park, “Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems,” Ieee Transactions On Very Large Scale Integration (Vlsi) Systems, vol. 24, no. 2, pp. 754–758, 2016. View at Publisher · View at Google Scholar
  • Juan Antonio Clemente, Ruben Gran, Abel Chocano, Carlos del Prado, and Javier Resano, “Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems,” Ieee Transactions On Very Large Scale Integration (Vlsi) Systems, vol. 24, no. 2, pp. 530–543, 2016. View at Publisher · View at Google Scholar
  • Agees Kumar C., Sivarani T.S., and Joseph Jawhar S., “Intensive random carrier pulse width modulation for induction motor drives based on hopping between discrete carrier frequencies,” IET Power Electronics, 2016. View at Publisher · View at Google Scholar
  • Anatolij Sergiyenko, and Anastasia Serhienko, “Modules for Pipelined Mixed Radix FFT Processors,” International Journal of Reconfigurable Computing, vol. 2016, pp. 1–7, 2016. View at Publisher · View at Google Scholar
  • A. Al-Wattar, S. Areibi, and G. Grewal, “An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable Systems,” International Journal of Reconfigurable Computing, vol. 2016, pp. 1–24, 2016. View at Publisher · View at Google Scholar
  • Rostam Affendi Hamzah, and Haidi Ibrahim, “Literature Survey on Stereo Vision Disparity Map Algorithms,” Journal of Sensors, vol. 2016, pp. 1–23, 2016. View at Publisher · View at Google Scholar
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  • Pascal Cotret, Guy Gogniat, and Martha Johanna Sepulveda, “Protection of heterogeneous architectures on FPGAs: An approach based on hardware firewalls,” Microprocessors and Microsystems, 2016. View at Publisher · View at Google Scholar
  • Omar Longoria-Gandara, Ramon Parra-Michel, Roberto Carrasco-Alvarez, and Eduardo Romero-Aguirre, “Iterative MIMO Detection and Channel Estimation Using Joint Superimposed and Pilot-Aided Training,” Mobile Information Systems, vol. 2016, pp. 1–11, 2016. View at Publisher · View at Google Scholar
  • Ismail San, Nuray At, Ibrahim Yakut, and Huseyin Polat, “Efficient paillier cryptoprocessor for privacy-preserving data mining,” Security and Communication Networks, 2016. View at Publisher · View at Google Scholar
  • Felix Siegle, Tanya Vladimirova, Jorgen Ilstad, and Omar Emam, “Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications,” Acm Computing Surveys, vol. 47, no. 2, 2015. View at Publisher · View at Google Scholar
  • Danilo Pani, Carlo Sau, Francesca Palumbo, and Luigi Raffo, “Computing Swarms for Self-Adaptiveness and Self-Organization in Floating-Point Array Processing,” Acm Transactions On Autonomous And Adaptive Systems, vol. 10, no. 3, 2015. View at Publisher · View at Google Scholar
  • Franck Yonga, Michael Mefenza, and Christophe Bobda, “ASP-Based Encoding Model of Architecture Synthesis for Smart Cameras in Distributed Networks,” ACM Transactions on Design Automation of Electronic Systems, vol. 20, no. 2, pp. 1–28, 2015. View at Publisher · View at Google Scholar
  • Dionysios Diamantopoulos, Kostas Siozios, Sotirios Xydis, and Dimitrios Soudris, “GENESIS: Parallel Application Placement onto Reconfigurable Architectures (Invited for the Special Issue on Runtime Management),” Acm Transactions On Embedded Computing Systems, vol. 14, no. 1, 2015. View at Publisher · View at Google Scholar
  • Daniele Palossi, Martino Ruggiero, and Luca Benini, “3D CV Descriptor on Parallel Heterogeneous Platforms,” ACM Transactions on Embedded Computing Systems, vol. 14, no. 4, pp. 1–25, 2015. View at Publisher · View at Google Scholar
  • Jo Vliegen, Nele Mentens, and Ingrid Verbauwhede, “Secure, Remote, Dynamic Reconfiguration of FPGAs,” Acm Transactions On Reconfigurable Technology And Systems, vol. 7, no. 4, 2015. View at Publisher · View at Google Scholar
  • Nuno Paulino, Joao Canas Ferreira, and Joao M. P. Cardoso, “A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses,” Acm Transactions On Reconfigurable Technology And Systems, vol. 7, no. 4, 2015. View at Publisher · View at Google Scholar
  • Daniel Llamocca, and Marios Pattichis, “Dynamic Energy, Performance, and Accuracy Optimization and Management Using Automatically Generated Constraints for Separable 2D FIR Filtering for Dig,” Acm Transactions On Reconfigurable Technology And Systems, vol. 7, no. 4, 2015. View at Publisher · View at Google Scholar
  • Tom Davidson, Elias Vansteenkiste, Karel Heyse, Karel Bruneel, and Dirk Stroobandt, “Identification of Dynamic Circuit Specialization Opportunities in RTL Code,” ACM Transactions on Reconfigurable Technology and Systems, vol. 8, no. 1, pp. 1–24, 2015. View at Publisher · View at Google Scholar
  • Ismael Seidel, Andre Beims Braescher, Marcio Monteiro, and Jose Luis Guentzel, “Towards optimal use of pel decimation to trade off quality for energy,” Analog Integrated Circuits And Signal Processing, vol. 85, no. 1, pp. 107–128, 2015. View at Publisher · View at Google Scholar
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  • Krzysztof J. Opieliński, Piotr Pruchnicki, Tadeusz Gudra, Przemysław Podgórski, Jacek Kurcz, Tomasz Kraśnicki, Marek Sąsiadek, and Jarosław Majewski, “Imaging Results of Multi-modal Ultrasound Computerized Tomography System Designed for Breast Diagnosis,” Computerized Medical Imaging and Graphics, 2015. View at Publisher · View at Google Scholar
  • François Duhem, Fabrice Muller, Robin Bonamy, and Sébastien Bilavarn, “FoRTReSS: a flow for design space exploration of partially reconfigurable systems,” Design Automation for Embedded Systems, 2015. View at Publisher · View at Google Scholar
  • Yier Jin, “Introduction to Hardware Security,” Electronics, vol. 4, no. 4, pp. 763–784, 2015. View at Publisher · View at Google Scholar
  • V. Sakthivel, and Elizabeth Elias, “Design of low complexity sharp MDFT filter banks with perfect reconstruction using hybrid harmony-gravitational search algorithm,” Engineering Science and Technology, an International Journal, 2015. View at Publisher · View at Google Scholar
  • Gokhan Polat, Sitki Ozturk, and Mehmet Yakut, “Design and Implementation of 256-Point Radix-4 100 Gbit/s FFT Algorithm into FPGA for High-Speed Applications,” ETRI Journal, vol. 37, no. 4, pp. 667–676, 2015. View at Publisher · View at Google Scholar
  • Jean-Philippe Diguet, Neil Bergmann, and Jean-Christophe Morgère, “Dedicated object processor for mobile augmented reality - sailor assistance case study,” EURASIP Journal on Embedded Systems, vol. 2015, no. 1, 2015. View at Publisher · View at Google Scholar
  • Runchun M. Wang, Tara J. Hamilton, Jonathan C. Tapson, and André van Schaik, “A neuromorphic implementation of multiple spike-timing synaptic plasticity rules for large-scale neural networks,” Frontiers in Neuroscience, vol. 9, 2015. View at Publisher · View at Google Scholar
  • Vinod Pangracious, Zied Marrakchi, and Habib Mehrez, “Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA,” IEEE Micro, vol. 35, no. 6, pp. 48–59, 2015. View at Publisher · View at Google Scholar
  • Roberto Sierra, Carlos Carreras, Gabriel Caffarena, and Carlos A. Lopez Barrio, “A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors,” Ieee Transactions On Computer-Aided Design Of Integrated Circuits And Systems, vol. 34, no. 1, pp. 52–62, 2015. View at Publisher · View at Google Scholar
  • Mieczyslaw Jessa, “On the Quality of Random Sequences Produced with a Combined Random Bit Generator,” Ieee Transactions On Computers, vol. 64, no. 3, pp. 791–804, 2015. View at Publisher · View at Google Scholar
  • Honorio Martin, Thomas Korak, Enrique San Millan, and Michael Hutter, “Fault Attacks on STRNGs: Impact of Glitches, Temperature, and Underpowering on Randomness,” Ieee Transactions On Information Forensics And Security, vol. 10, no. 2, pp. 266–277, 2015. View at Publisher · View at Google Scholar
  • Bojan Jovanovic, Raphael M. Brum, and Lionel Torres, “Comparative Analysis of MTJ/CMOS Hybrid Cells Based on TAS and In-Plane STT Magnetic Tunnel Junctions,” Ieee Transactions On Magnetics, vol. 51, no. 2, 2015. View at Publisher · View at Google Scholar
  • Heather Quinn, and Michael Wirthlin, “Validation Techniques for Fault Emulation of SRAM-based FPGAs,” Ieee Transactions On Nuclear Science, vol. 62, no. 4, pp. 1487–1500, 2015. View at Publisher · View at Google Scholar
  • Enrique Canto-Navarro, Mariano Lopez-Garcia, Rafael Ramos-Lara, and Raul Sanchez-Reillo, “Flexible Biometric Online Speaker-Verification System Implemented on FPGA Using Vector Floating-Point Units,” Ieee Transactions On Very Large Scale Integration (Vlsi) Systems, vol. 23, no. 11, pp. 2497–2507, 2015. View at Publisher · View at Google Scholar
  • Qiang Liu, Wenqing Ji, Qi Chen, and Terrence Mak, “IP Protection of Mesh NoCs Using Square Spiral Routing,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1–1, 2015. View at Publisher · View at Google Scholar
  • Jorge Gonzalez-Dominguez, Lars Wienbrandt, Jan Christian Kassens, David Ellinghaus, Manfred Schimmler, and Bertil Schmidt, “Parallelizing Epistasis Detection in GWAS on FPGA and GPU-Accelerated Computing Systems,” IEEE/ACM Transactions on Computational Biology and Bioinformatics, vol. 12, no. 5, pp. 982–994, 2015. View at Publisher · View at Google Scholar
  • Zhen Yang, Chuanzeng Liang, Jian Wang, and Jinmei Lai, “A new automatic method for testing interconnect resources in FPGAs based on general routing matrix,” Ieice Electronics Express, vol. 12, no. 20, 2015. View at Publisher · View at Google Scholar
  • Weiguo Wu, Shiqiang Nie, Chaohui Wang, and Depei Qian, “BFT: a placement algorithm for non-rectangle task model in reconfigurable computing system,” IET Computers & Digital Techniques, 2015. View at Publisher · View at Google Scholar
  • Nuno Neves, Henrique Mendes, Ricardo Jorge Chaves, Pedro Tomas, and Nuno Roma, “Morphable hundred-core heterogeneous architecture for energy-aware computation,” Iet Computers And Digital Techniques, vol. 9, no. 1, pp. 49–62, 2015. View at Publisher · View at Google Scholar
  • Hermann Seuschek, Piyush Khurana, and Georg Sigl, “HiPeC — High Performance Cryptographic Service for Heterogeneous Network-on-Chip Systems,” IFAC-PapersOnLine, vol. 48, no. 4, pp. 31–36, 2015. View at Publisher · View at Google Scholar
  • Martín Vázquez, and Elías Todorovich, “FPGA-specific decimal sign-magnitude addition and subtraction,” International Journal of Electronics, pp. 1–20, 2015. View at Publisher · View at Google Scholar
  • Luis Andres Cardona, and Carles Ferrer, “AC_ICAP: A Flexible High Speed ICAP Controller,” International Journal of Reconfigurable Computing, vol. 2015, pp. 1–15, 2015. View at Publisher · View at Google Scholar
  • Carlos A. Zerbini, and Jorge M. Finochietto, “Optimization of Lookup Schemes for Flow-Based Packet Classification on FPGAs,” International Journal of Reconfigurable Computing, vol. 2015, pp. 1–31, 2015. View at Publisher · View at Google Scholar
  • Tobias Kenter, Henning Schmitz, and Christian Plessl, “Exploring Trade-Offs between Specialized Dataflow Kernels and a Reusable Overlay in a Stereo Matching Case Study,” International Journal of Reconfigurable Computing, vol. 2015, pp. 1–24, 2015. View at Publisher · View at Google Scholar
  • Jonas Gomes Filho, Marius Strum, and Wang Jiang Chau, “Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems,” International Journal of Reconfigurable Computing, vol. 2015, pp. 1–13, 2015. View at Publisher · View at Google Scholar
  • Erich Wenger, and Paul Wolfger, “Harder, better, faster, stronger: elliptic curve discrete logarithm computations on FPGAs,” Journal of Cryptographic Engineering, 2015. View at Publisher · View at Google Scholar
  • Ali Akbar Zarezadeh, Christophe Bobda, Franck Yonga, and Michael Mefenza, “Efficient network clustering for traffic reduction in embedded smart camera networks,” Journal of Real-Time Image Processing, 2015. View at Publisher · View at Google Scholar
  • Ricardo Ferreira, Waldir Denver, Monica Pereira, Stephan Wong, Carlos A. Lisbȏa, and Luigi Carro, “A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility,” Journal of Signal Processing Systems, 2015. View at Publisher · View at Google Scholar
  • Nehal N. Shah, and Upena D. Dalal, “Hardware Efficient Double Diamond Search Block Matching Algorithm for Fast Video Motion Estimation,” Journal of Signal Processing Systems, 2015. View at Publisher · View at Google Scholar
  • Shaoteng Liu, Axel Jantsch, and Zhonghai Lu, “MultiCS: Circuit Switched NoC with Multiple Sub-Networks and Sub-Channels,” Journal of Systems Architecture, 2015. View at Publisher · View at Google Scholar
  • Carlos H. Llanos, Ronald H. Hurtado, and Sadek C. Absi Alfaro, “FPGA-based approach for change detection in GTAW welding process,” Journal of the Brazilian Society of Mechanical Sciences and Engineering, 2015. View at Publisher · View at Google Scholar
  • Arlindo R. Galvão Filho, Lauro C. Martins de Paula, Clarimar José Coelho, Telma Woerle de Lima, and Anderson da Silva Soares, “CUDA parallel programming for simulation of epidemiological models based on individuals,” Mathematical Methods in the Applied Sciences, 2015. View at Publisher · View at Google Scholar
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  • Mark Hamilton, and William P. Marnane, “Implementation of a Secure TLS Coprocessor on an FPGA,” Microprocessors and Microsystems, 2015. View at Publisher · View at Google Scholar
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