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Citations to this Journal [156 citations: 1–100 of 142 articles]

Articles published in International Journal of Reconfigurable Computing have been cited 156 times. The following is a list of the 142 articles that have cited the articles published in International Journal of Reconfigurable Computing.

  • Runchun M. Wang, Tara J. Hamilton, Jonathan C. Tapson, and André van Schaik, “A mixed-signal implementation of a polychronous spiking neural network with delay adaptation,” Frontiers in Neuroscience, vol. 8, 2014. View at Publisher · View at Google Scholar
  • Shuguo Li, “A Digital TRNG Based on Cross Feedback Ring Oscillators,” Ieice Transactions on Fundamentals of Electronics Communications and Comput, vol. E97A, no. 1, pp. 284–291, 2014. View at Publisher · View at Google Scholar
  • Hamad Marzouqi, and Mahmoud Al-Qutayri, “Review of gate-level differential power analysis and fault analysis counter measures,” Iet Information Security, vol. 8, no. 1, pp. 51–66, 2014. View at Publisher · View at Google Scholar
  • Ali Emre Pusane, and Gunhan Dundar, “A novel design method for discrete time chaos based true random number gene rators,” Integration-The Vlsi Journal, vol. 47, no. 1, pp. 38–47, 2014. View at Publisher · View at Google Scholar
  • Tim Todman, Stephan Stilkerich, and Wayne Luk, “Using Statistical Assertions to Guide Self-Adaptive Systems,” International Journal of Reconfigurable Computing, vol. 2014, pp. 1–8, 2014. View at Publisher · View at Google Scholar
  • B. Jovanović, R. M. Brum, and L. Torres, “A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design,” Journal of Applied Physics, vol. 115, no. 13, pp. 134316, 2014. View at Publisher · View at Google Scholar
  • Wei Guo, Guillaume Prenat, and Bernard Dieny, “A novel architecture of non-volatile magnetic arithmetic logic unit using magnetic tunnel junctions,” Journal of Physics D: Applied Physics, vol. 47, no. 16, pp. 165001, 2014. View at Publisher · View at Google Scholar
  • Dario Socci, and Nicola Mazzocca, “ASP-based optimized mapping in a simulink-to-MPSoC design flow,” Journal of Systems Architecture, vol. 60, no. 1, pp. 108–118, 2014. View at Publisher · View at Google Scholar
  • Robert Brumnik, Vladislav Kovtun, Andrew Okhrimenko, and Sergii Kavun, “Techniques for Performance Improvement of Integer Multiplication in Cryptographic Applications,” Mathematical Problems in Engineering, vol. 2014, pp. 1–7, 2014. View at Publisher · View at Google Scholar
  • Ludovic Devaux, and Sebastien Pillement, “OCEAN, a flexible adaptive Network-On-Chip for dynamic applications,” Microprocessors and Microsystems, 2014. View at Publisher · View at Google Scholar
  • Loïc Lagadec, Ciprian Teodorov, Jean-Christophe Le Lann, Damien Picard, and Erwan Fabiani, “Model-driven Toolset for Embedded Reconfigurable Cores: Flexible Prototyping and Software-like Debugging,” Science of Computer Programming, 2014. View at Publisher · View at Google Scholar
  • Javier Hormigo, Juan P. Oliver, and Eduardo Boemo, “Self-Reconfigurable Constant Multiplier for FPGA,” Acm Transactions on Reconfigurable Technology and Systems, vol. 6, no. 3, 2013. View at Publisher · View at Google Scholar
  • Pao-Ann Hsiung, “Virtualizable Hardware/Software Design Infrastructure for Dynamically Parti ally Reconfigurable Systems,” Acm Transactions On Reconfigurable Technology And Systems, vol. 6, no. 2, 2013. View at Publisher · View at Google Scholar
  • Hanyu Liu, and Senthilkumar T. Rajavel, “Integration of Net-Length Factor with Timing- and Routability-Driven Cluste ring Algorithms,” Acm Transactions on Reconfigurable Technology and Systems, vol. 6, no. 3, 2013. View at Publisher · View at Google Scholar
  • Yamuna Rajasekhar, and Ron Sass, “Architecture and applications for an All-FPGA parallel computer,” Cluster Computing, 2013. View at Publisher · View at Google Scholar
  • E. Ostua, J. Juan, M. J. Bellido, J. Viejo, and D. Guerrero, “NanoFS: a hardware-oriented file system,” Electronics Letters, vol. 49, no. 19, 2013. View at Publisher · View at Google Scholar
  • Konrad Moeller, Uwe Meyer-Baese, Diana Fanghaenel, and Peter Zipf, “FIR filter optimization for video processing on FPGAs,” Eurasip Journal On Advances In Signal Processing, 2013. View at Publisher · View at Google Scholar
  • Daniel Llamocca, and Marios Pattichis, “A Dynamically Reconfigurable Pixel Processor System Based on Power/Energy-P erformance-Accuracy Optimization,” Ieee Transactions on Circuits and Systems for Video Technology, vol. 23, no. 3, pp. 488–502, 2013. View at Publisher · View at Google Scholar
  • Chang-Hsiung Tsai, “A Quick Pessimistic Diagnosis Algorithm for Hypercube-Like Multiprocessor S ystems under the PMC Model,” Ieee Transactions on Computers, vol. 62, no. 2, pp. 259–267, 2013. View at Publisher · View at Google Scholar
  • Roger Woods, Richard Veitch, and Scott Fischaber, “Optimization of Weighted Finite State Transducer for Speech Recognition,” Ieee Transactions On Computers, vol. 62, no. 8, pp. 1607–1615, 2013. View at Publisher · View at Google Scholar
  • Rizwan A. Ashraf, and Ronald F. Demara, “Scalable FPGA refurbishment using netlist-driven evolutionary algorithms,” IEEE Transactions on Computers, vol. 62, no. 8, pp. 1526–1541, 2013. View at Publisher · View at Google Scholar
  • Tughrul Arslan, Jon Perez, Khaled Benkrid, Ali Ebrahim, Chuan Hong, Raul Torrego, and Imanol Martinez, “R3TOS: A Novel Reliable Reconfigurable Real-Time Operating System for Highl y Adaptive, Efficient, and Dependable Computing on FPGAs,” Ieee Transactions On Computers, vol. 62, no. 8, pp. 1542–1556, 2013. View at Publisher · View at Google Scholar
  • Rabie Ben Atitallah, Eric Senn, Daniel Chillet, Mickael Lanoe, and Dominique Blouin, “An Efficient Framework for Power-Aware Design of Heterogeneous MPSoC,” Ieee Transactions On Industrial Informatics, vol. 9, no. 1, pp. 487–501, 2013. View at Publisher · View at Google Scholar
  • Stephen P. Buchner, Dolores A. Black, and William H. Robinson, “Fault Simulation and Emulation Tools to Augment Radiation-Hardness Assuranc e Testing,” Ieee Transactions On Nuclear Science, vol. 60, no. 3, pp. 2119–2142, 2013. View at Publisher · View at Google Scholar
  • G. Drake, W. S. Fernando, and R. W. Stanek, “Modulator-Based, High Bandwidth Optical Links for HEP Experiments,” Ieee Transactions on Nuclear Science, vol. 60, no. 5, pp. 3497–3501, 2013. View at Publisher · View at Google Scholar
  • Jim Harkin, Liam J. McDaid, Fearghal Morgan, Sandeep Pande, Seamus Cawley, and Brian McGinley, “Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Netwo rk Hardware Implementations,” Ieee Transactions on Parallel and Distributed Systems, vol. 24, no. 12, pp. 2451–2461, 2013. View at Publisher · View at Google Scholar
  • Dajiang Liu, Shaojun Wei, and Leibo Liu, “Affine Transformations for Communication and Reconfiguration Optimization o f Mapping Loop Nests on CGRAs,” Ieice Transactions On Information And Systems, vol. E96D, no. 8, pp. 1582–1591, 2013. View at Publisher · View at Google Scholar
  • Wei Chen, and Richard P. Mied, “Optical flow estimation for motion-compensated compression,” Image and Vision Computing, vol. 31, no. 3, pp. 275–289, 2013. View at Publisher · View at Google Scholar
  • Pedrino, Roda, Kato, Saito, Tronco, Tsunaki, Morandin Jr., and Nicoletti, “A genetic programming based system for the automatic construction of image filters,” Integrated Computer-Aided Engineering, vol. 20, no. 3, pp. 275–287, 2013. View at Publisher · View at Google Scholar
  • Placido Rogerio Pinheiro, Álvaro Meneses Sobreira Neto, and Alexei Barbosa Aguiar, “Handing Optimization Energy Consumption in Heterogeneous Wireless Sensor Networks,” International Journal of Distributed Sensor Networks, vol. 2013, pp. 1–9, 2013. View at Publisher · View at Google Scholar
  • O. Ahmed, S. Areibi, R. Collier, and G. Grewal, “An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization,” International Journal of Reconfigurable Computing, vol. 2013, pp. 1–23, 2013. View at Publisher · View at Google Scholar
  • Malte Baesler, and Sven-Ole Voigt, “Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs,” International Journal of Reconfigurable Computing, vol. 2013, pp. 1–16, 2013. View at Publisher · View at Google Scholar
  • Ahmed, Areibi, and Grewal, “Hardware accelerators targeting a novel group based packet classification algorithm,” International Journal of Reconfigurable Computing, vol. 2013, 2013. View at Publisher · View at Google Scholar
  • Krzysztof Jozwik, Shinya Honda, Masato Edahiro, Hiroyuki Tomiyama, and Hiroaki Takada, “Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs,” International Journal of Reconfigurable Computing, vol. 2013, pp. 1–40, 2013. View at Publisher · View at Google Scholar
  • Chuan Hong, Ali Ebrahim, Tughrul Arslan, Imanol Martinez, Xabier Iturbe, and Khaled Benkrid, “Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence,” International Journal of Reconfigurable Computing, vol. 2013, pp. 1–32, 2013. View at Publisher · View at Google Scholar
  • Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang, and Jinian Bian, “Unification Of Pr Region Floorplanning And Fine-Grained Placement For Dynam Ic Partially Reconfigurable Fpgas,” Journal of Circuits Systems and Computers, vol. 22, no. 4, 2013. View at Publisher · View at Google Scholar
  • George S. Athanasiou, Harris E. Michail, Takis Kasparis, and Costas E. Goutis, “A Systematic Flow For Developing Totally Self-Checking Architectures For Sh A-1 And Sha-2 Cryptographic Hash Families,” Journal Of Circuits Systems And Computers, vol. 22, no. 6, 2013. View at Publisher · View at Google Scholar
  • Bouraoui Ouni, and Abdellatif Mtibaa, “Online scheduling and placement of hardware modules on partially dynamic architectures,” Journal of Circuits, Systems and Computers, vol. 22, no. 3, 2013. View at Publisher · View at Google Scholar
  • Yanqin Bai, and Chuanhao Guo, “Doubly nonnegative relaxation method for solving multiple objective quadratic programming problems,” Journal of Industrial and Management Optimization, vol. 10, no. 2, pp. 543–556, 2013. View at Publisher · View at Google Scholar
  • Shih-An Li, Ching-Yi Chen, and Ching-Han Chen, “Design of a shift-and-add based hardware accelerator for color space conversion,” Journal of Real-Time Image Processing, 2013. View at Publisher · View at Google Scholar
  • Sol Pedre, Tomáš Krajník, Elías Todorovich, and Patricia Borensztejn, “Accelerating embedded image processing for real time: a case study,” Journal of Real-Time Image Processing, 2013. View at Publisher · View at Google Scholar
  • Yusuf Aksehir, Kamil Erdayandi, Tevfik Zafer Ozcan, and Ilker Hamzaoglu, “A low energy adaptive motion estimation hardware for H.264 multiview video coding,” Journal of Real-Time Image Processing, 2013. View at Publisher · View at Google Scholar
  • Rafael Ramos-Lara, Mariano Lopez-Garcia, Enrique Canto-Navarro, and Luis Puente-Rodriguez, “Real-Time Speaker Verification System Implemented on Reconfigurable Hardwar e,” Journal Of Signal Processing Systems For Signal Image And Video Technology, vol. 71, no. 2, pp. 89–103, 2013. View at Publisher · View at Google Scholar
  • Alexandra Aguiar, Sergio Johann Filho, Felipe Magalhaes, and Fabiano Hessel, “On the design space exploration through the Hellfire Framework,” Journal of Systems Architecture, 2013. View at Publisher · View at Google Scholar
  • Shin-Yan Chiou, “Authenticated Blind Issuing of Symmetric Keys for Mobile Access Control System without Trusted Parties,” Mathematical Problems in Engineering, vol. 2013, pp. 1–11, 2013. View at Publisher · View at Google Scholar
  • F. Duhem, N. Marques, F. Muller, H. Rabah, S. Weber, and P. Lorenzini, “Dynamically reconfigurable entropy coder for multi-standard video adaptatio n using FaRM,” Microprocessors And Microsystems, vol. 37, no. 1, pp. 1–8, 2013. View at Publisher · View at Google Scholar
  • Chiraz Trabelsi, Samy Meftali, and Jean-Luc Dekeyser, “Decentralized control for dynamically reconfigurable FPGA systems,” Microprocessors and Microsystems, 2013. View at Publisher · View at Google Scholar
  • Onur Derin, Emanuele Cannella, Giuseppe Tuveri, Paolo Meloni, Todor Stefanov, Leandro Fiorin, Luigi Raffo, and Mariagiovanna Sami, “A System-level Approach to Adaptivity and Fault-tolerance in NoC-based MPSoCs: the MADNESS Project,” Microprocessors and Microsystems, 2013. View at Publisher · View at Google Scholar
  • Tomyslav Sledevič, and Liudas Stašionis, “Lietuvių kalbos Pavienių žodžių atpažinimo algoritmo įgyvendinimas LAUKU Programuojama Logine Matrica,” Mokslas - Lietuvos ateitis, vol. 5, no. 2, pp. 101–104, 2013. View at Publisher · View at Google Scholar
  • J.A. Scott Kelso, Guillaume Dumas, and Emmanuelle Tognoli, “Outline of a general theory of behavior and brain coordination,” Neural Networks, vol. 37, pp. 120–131, 2013. View at Publisher · View at Google Scholar
  • Fearghal Morgan, Gerard Smit, Tom Bruintjes, Jochem Rutgers, Brian McGinley, Seamus Cawley, Jim Harkin, and Liam McDaid, “Fixed latency on-chip interconnect for hardware spiking neural network arch itectures,” Parallel Computing, vol. 39, no. 9, pp. 357–371, 2013. View at Publisher · View at Google Scholar
  • David P. Rosin, Damien Rontani, and Daniel J. Gauthier, “Ultrafast physical generation of random numbers using hybrid Boolean networks,” Physical Review E, vol. 87, no. 4, 2013. View at Publisher · View at Google Scholar
  • Ricardo Finger, Patricio Mena, Nicolas Reyes, Rafael Rodriguez, and Leonardo Bronfman, “A Calibrated Digital Sideband Separating Spectrometer for Radio Astronomy A pplications,” Publications of The Astronomical Society of The Pacific, vol. 125, no. 925, pp. 263–269, 2013. View at Publisher · View at Google Scholar
  • Rong Ren, Jianguo Wei, Eduardo Juarez, Matias Garrido, Cesar Sanz, and Fernando Pescador, “A PMC-driven Methodology for Energy Estimation in RVC-CAL Video Codec Specifications,” Signal Processing: Image Communication, 2013. View at Publisher · View at Google Scholar
  • Kostas Siozios, Vasilis F. Pavlidis, and Dimitrios Soudris, “A Novel Framework for Exploring 3-D FPGAs with Heterogeneous Interconnect F abric,” Acm Transactions On Reconfigurable Technology And Systems, vol. 5, no. 1, 2012. View at Publisher · View at Google Scholar
  • Gustavo Sanchez, Marcel Corrêa, Diego Noble, Marcelo Porto, Sergio Bampi, and Luciano Agostini, “Hardware design focusing in the tradeoff cost versus quality for the H.264/AVC fractional motion estimation targeting high definition videos,” Analog Integrated Circuits and Signal Processing, vol. 73, no. 3, pp. 931–944, 2012. View at Publisher · View at Google Scholar
  • Teemu Pitkänen, Peter Jamieson, Tobias Becker, Sami Moisio, and Jarmo Takala, “Power consumption benchmarking for reconfigurable platforms,” Analog Integrated Circuits and Signal Processing, vol. 73, no. 2, pp. 649–659, 2012. View at Publisher · View at Google Scholar
  • Martin Gebser, Benjamin Kaufmann, and Torsten Schaub, “Conflict-driven answer set solving: From theory to practice,” Artificial Intelligence, vol. 187-188, pp. 52–89, 2012. View at Publisher · View at Google Scholar
  • Stefan Wildermann, Felix Reimann, Daniel Ziener, and Jürgen Teich, “Symbolic system-level design methodology for multi-mode reconfigurable systems,” Design Automation for Embedded Systems, 2012. View at Publisher · View at Google Scholar
  • Samya Elaoud, Yassine Aoudni, Jean-Francois Nezan, and Mohamed Abid, “An efficient Resource Management to optimize the placement of hardware task on FPGA in the RVC framework,” Design Automation for Embedded Systems, vol. 16, no. 4, pp. 363–380, 2012. View at Publisher · View at Google Scholar
  • Vaibhav Garg, Ravi Shekhar, and John G. Harris, “Spiking Neuron Computation With the Time Machine,” Ieee Transactions On Biomedical Circuits And Systems, vol. 6, no. 2, pp. 142–155, 2012. View at Publisher · View at Google Scholar
  • ChiWai Yu, Alastair M. Smith, Wayne Luk, Philip H. W. Leong, and Steven J. E. Wilton, “Optimizing Floating Point Units in Hybrid FPGAs,” Ieee Transactions on Very Large Scale Integration (vlsi) Systems, vol. 20, no. 7, pp. 1295–1303, 2012. View at Publisher · View at Google Scholar
  • Yoshihiro Ichinomiya, Tsuyoshi Kimura, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, and Toshinori Sueyoshi, “Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Bas ed Partial Reconfiguration,” Ieice Transactions on Fundamentals of Electronics Communications and Comput, vol. E95A, no. 12, pp. 2347–2356, 2012. View at Publisher · View at Google Scholar
  • Shingo Yoshizawa, and Yoshikazu Miyanaga, “Design of Area- and Power-Efficient Pipeline FFT Processors for 8x8 MIMO-OF DM Systems,” Ieice Transactions on Fundamentals of Electronics Communications and Comput, vol. E95A, no. 2, pp. 550–558, 2012. View at Publisher · View at Google Scholar
  • Kazuki Inoue, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, and Toshinori Sueyoshi, “An Easily Testable Routing Architecture and Prototype Chip,” Ieice Transactions On Information And Systems, vol. E95D, no. 2, pp. 303–313, 2012. View at Publisher · View at Google Scholar
  • Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, and Takashi Ishiguro, “A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks,” Ieice Transactions On Information And Systems, vol. E95D, no. 2, pp. 324–334, 2012. View at Publisher · View at Google Scholar
  • Hisashi Hata, and Shuichi Ichiawa, “FPGA Implementation of Metastability-Based True Random Number Generator,” Ieice Transactions On Information And Systems, vol. E95D, no. 2, pp. 426–436, 2012. View at Publisher · View at Google Scholar
  • F. Duhem, F. Muller, and P. Lorenzini, “Reconfiguration time overhead on field programmable gate arrays: reduction and cost model,” Iet Computers And Digital Techniques, vol. 6, no. 2, pp. 105–113, 2012. View at Publisher · View at Google Scholar
  • S. Gao, D. Al-Khalili, N. Chabini, and P. Langlois, “Asymmetric large size multipliers with optimised FPGA resource utilisation,” Iet Computers And Digital Techniques, vol. 6, no. 6, pp. 372–383, 2012. View at Publisher · View at Google Scholar
  • Placido Rogerio Pinheiro, Andre Luis Vasconcelos Coelho, Alexei Barbosa Aguiar, and Alvaro de Menezes Sobreira Neto, “Towards Aid by Generate and Solve Methodology: Application in the Problem of Coverage and Connectivity in Wireless Sensor Networks,” International Journal of Distributed Sensor Networks, vol. 2012, pp. 1–11, 2012. View at Publisher · View at Google Scholar
  • Hanaa M. Hussain, Khaled Benkrid, Ali Ebrahim, Ahmet T. Erdogan, and Huseyin Seker, “Novel dynamic partial reconfiguration implementation of K-means clustering on FPGAs: Comparative results with GPPs and GPUs,” International Journal of Reconfigurable Computing, vol. 2012, 2012. View at Publisher · View at Google Scholar
  • Jones Y. Mori, Janier Arias-Garcia, Camilo Sánchez-Ferreira, Daniel M. Muñoz, Carlos H. Llanos, and J. M. S. T. Motta, “An FPGA-Based Omnidirectional Vision Sensor for Motion Detection on Mobile Robots,” International Journal of Reconfigurable Computing, vol. 2012, pp. 1–16, 2012. View at Publisher · View at Google Scholar
  • Gustavo Sanchez, Felipe Sampaio, Marcelo Porto, Sergio Bampi, and Luciano Agostini, “DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation,” International Journal of Reconfigurable Computing, vol. 2012, pp. 1–12, 2012. View at Publisher · View at Google Scholar
  • Ra Inta, David J. Bowman, and Susan M. Scott, “The “Chimera”: An Off-The-Shelf CPU/GPGPU/FPGA Hybrid Computing Platform,” International Journal of Reconfigurable Computing, vol. 2012, pp. 1–10, 2012. View at Publisher · View at Google Scholar
  • Lukas Meder, Stephan Werner, Oliver Oey, Jürgen Becker, Michael Hübner, and Diana Göhringer, “Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration,” International Journal of Reconfigurable Computing, vol. 2012, pp. 1–14, 2012. View at Publisher · View at Google Scholar
  • Christian de Schryver, Daniel Schmidt, Norbert Wehn, Elke Korn, Henning Marxen, Anton Kostiuk, and Ralf Korn, “A Hardware Efficient Random Number Generator for Nonuniform Distributions with Arbitrary Precision,” International Journal of Reconfigurable Computing, vol. 2012, pp. 1–11, 2012. View at Publisher · View at Google Scholar
  • Kaveh Aasaraai, and Andreas Moshovos, “NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution,” International Journal of Reconfigurable Computing, vol. 2012, pp. 1–12, 2012. View at Publisher · View at Google Scholar
  • Yi Zhan, and Tadahiro Kuroda, “Wearable sensor-based human activity recognition from environmental background sounds,” Journal of Ambient Intelligence and Humanized Computing, 2012. View at Publisher · View at Google Scholar
  • Yousri Ouerhani, Maher Jridi, and Ayman Alfalou, “Area-Delay Efficient Fft Architecture Using Parallel Processing And New Mem Ory Sharing Technique,” Journal Of Circuits Systems And Computers, vol. 21, no. 6, 2012. View at Publisher · View at Google Scholar
  • Jintao Yu, Jianmin Pang, Zheng Shan, and Haoran Guo, “On-the-fly data transmission for FPGA acceleration: A case study,” Journal of Convergence Information Technology, vol. 7, no. 19, pp. 418–425, 2012. View at Publisher · View at Google Scholar
  • John A. Kalomiros, “Dense disparity features for fast stereo vision,” Journal of Electronic Imaging, vol. 21, no. 4, 2012. View at Publisher · View at Google Scholar
  • Sardar Anisul Haque, and Marc Moreno Maza, “Plain polynomial arithmetic on GPU,” Journal of Physics: Conference Series, vol. 385, no. 1, 2012. View at Publisher · View at Google Scholar
  • Matthias Birk, Michael Zapf, Matthias Balzer, Nicole Ruiter, and Jürgen Becker, “A comprehensive comparison of GPU- and FPGA-based acceleration of reflection image reconstruction for 3D ultrasound computer tomography,” Journal of Real-Time Image Processing, vol. 9, no. 1, pp. 159–170, 2012. View at Publisher · View at Google Scholar
  • Pierre-Henri Horrein, Christine Hennebert, and Frédéric Pétrot, “An environment for (re)configuration and execution management of heterogeneous flexible radio platforms,” Microprocessors and Microsystems, 2012. View at Publisher · View at Google Scholar
  • Snaider Carrillo, Jim Harkin, Liam McDaid, Sandeep Pande, Seamus Cawley, Brian McGinley, and Fearghal Morgan, “Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers,” Neural Networks, vol. 33, pp. 42–57, 2012. View at Publisher · View at Google Scholar
  • Andrew G. Schmidt, Siddhartha Datta, Ashwin A. Mendon, and Ron Sass, “Investigation into scaling I/O bound streaming applications productively with an all-FPGA cluster,” Parallel Computing, vol. 38, no. 8, pp. 344–364, 2012. View at Publisher · View at Google Scholar
  • Emanuele Cannella, Onur Derin, Paolo Meloni, Giuseppe Tuveri, and Todor Stefanov, “Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks,” VLSI Design, vol. 2012, pp. 1–17, 2012. View at Publisher · View at Google Scholar
  • Emanuele Cannella, Lorenzo Di Gregorio, Leandro Fiorin, Menno Lindwer, Paolo Melonr, Olaf Neugebauer, and Andy Pimentel, “Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?,” 2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2011, pp. 120–129, 2011. View at Publisher · View at Google Scholar
  • Ekaterina Gonina, Gerald Friedland, Henry Cook, and Kurt Keutzer, “Fast speaker diarization using a high-level scripting language,” 2011 IEEE Workshop on Automatic Speech Recognition and Understanding, ASRU 2011, Proceedings, pp. 553–558, 2011. View at Publisher · View at Google Scholar
  • Ikbel Belaid, Fabrice Muller, and Maher Benjemaa, “Optimal static scheduling of real-time dependent tasks on reconfigurable hardware devices,” 2011 International Conference on Communications, Computing and Control Applications, CCCA 2011, 2011. View at Publisher · View at Google Scholar
  • Martin Kumm, and Peter Zipf, “High speed low complexity FPGA-based FIR filters using pipelined adder graphs,” 2011 International Conference on Field-Programmable Technology, FPT 2011, 2011. View at Publisher · View at Google Scholar
  • Gian Carlo Cardarilli, Marco Re, Ilir Shuli, and Lorenzo Simone, “Partial reconfiguration in the implementation of autonomous radio receivers for space,” 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2011 - Proceedings, 2011. View at Publisher · View at Google Scholar
  • Hung-Manh Pham, Ludovic Devaux, and Sébastien Pillement, “Re2DA: Reliable and reconfigurable dynamic architecture,” 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2011 - Proceedings, 2011. View at Publisher · View at Google Scholar
  • Scott Lloyd, and Quinn O. Snell, “Accelerated large-scale multiple sequence alignment,” Bmc Bioinformatics, vol. 12, 2011. View at Publisher · View at Google Scholar
  • Noor Elaiza Abdul Khalid, Norharyati Md Ariff, Saadiah Yahya, and Noorhayati Mohamed Noor, “A review of bio-inspired algorithms as image processing techniques,” Communications in Computer and Information Science, vol. 179, no. 1, pp. 660–673, 2011. View at Publisher · View at Google Scholar
  • Matthias Birk, Alexander Guth, Michael Zapf, Matthias Balzer, Nicole Ruiter, Michael Hübner, and Jürgen Becker, “Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing,” Conference on Design and Architectures for Signal and Image Processing, DASIP, pp. 67–74, 2011. View at Publisher · View at Google Scholar
  • Emanuele Cannella, Onur Derin, and Todor Stefanov, “Middleware approaches for adaptivity of Kahn process networks on networks-on-chip,” Conference on Design and Architectures for Signal and Image Processing, DASIP, pp. 100–107, 2011. View at Publisher · View at Google Scholar
  • Bertrand Le Gal, and Emmanuel Casseau, “Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design,” Eurasip Journal on Advances in Signal Processing, 2011. View at Publisher · View at Google Scholar
  • Ruben Salvador, Felix Moreno, Teresa Riesgo, and Lukas Sekanina, “Evolutionary Approach to Improve Wavelet Transforms for Image Compression i n Embedded Systems,” Eurasip Journal on Advances in Signal Processing, 2011. View at Publisher · View at Google Scholar
  • Seamus Cawley, Fearghal Morgan, Brian McGinley, Sandeep Pande, Liam McDaid, Snaider Carrillo, and Jim Harkin, “Hardware spiking neural network prototyping and application,” Genetic Programming and Evolvable Machines, vol. 12, no. 3, pp. 257–280, 2011. View at Publisher · View at Google Scholar