About this Journal Submit a Manuscript Table of Contents

Citations to this Journal [221 citations: 1–100 of 200 articles]

Articles published in International Journal of Reconfigurable Computing have been cited 221 times. The following is a list of the 200 articles that have cited the articles published in International Journal of Reconfigurable Computing.

  • Felix Siegle, Tanya Vladimirova, Jorgen Ilstad, and Omar Emam, “Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications,” Acm Computing Surveys, vol. 47, no. 2, 2015. View at Publisher · View at Google Scholar
  • Franck Yonga, Michael Mefenza, and Christophe Bobda, “ASP-Based Encoding Model of Architecture Synthesis for Smart Cameras in Distributed Networks,” ACM Transactions on Design Automation of Electronic Systems, vol. 20, no. 2, pp. 1–28, 2015. View at Publisher · View at Google Scholar
  • Dionysios Diamantopoulos, Kostas Siozios, Sotirios Xydis, and Dimitrios Soudris, “GENESIS: Parallel Application Placement onto Reconfigurable Architectures (Invited for the Special Issue on Runtime Management),” Acm Transactions On Embedded Computing Systems, vol. 14, no. 1, 2015. View at Publisher · View at Google Scholar
  • Jo Vliegen, Nele Mentens, and Ingrid Verbauwhede, “Secure, Remote, Dynamic Reconfiguration of FPGAs,” Acm Transactions On Reconfigurable Technology And Systems, vol. 7, no. 4, 2015. View at Publisher · View at Google Scholar
  • Nuno Paulino, Joao Canas Ferreira, and Joao M. P. Cardoso, “A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses,” Acm Transactions On Reconfigurable Technology And Systems, vol. 7, no. 4, 2015. View at Publisher · View at Google Scholar
  • Daniel Llamocca, and Marios Pattichis, “Dynamic Energy, Performance, and Accuracy Optimization and Management Using Automatically Generated Constraints for Separable 2D FIR Filtering for Dig,” Acm Transactions On Reconfigurable Technology And Systems, vol. 7, no. 4, 2015. View at Publisher · View at Google Scholar
  • Tom Davidson, Elias Vansteenkiste, Karel Heyse, Karel Bruneel, and Dirk Stroobandt, “Identification of Dynamic Circuit Specialization Opportunities in RTL Code,” ACM Transactions on Reconfigurable Technology and Systems, vol. 8, no. 1, pp. 1–24, 2015. View at Publisher · View at Google Scholar
  • Arnab Kumar Biswas, S. K. Nandy, and Ranjani Narayan, “Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat,” Circuits, Systems, and Signal Processing, 2015. View at Publisher · View at Google Scholar
  • Krzysztof J. Opieliński, Piotr Pruchnicki, Tadeusz Gudra, Przemysław Podgórski, Jacek Kurcz, Tomasz Kraśnicki, Marek Sąsiadek, and Jarosław Majewski, “Imaging Results of Multi-modal Ultrasound Computerized Tomography System Designed for Breast Diagnosis,” Computerized Medical Imaging and Graphics, 2015. View at Publisher · View at Google Scholar
  • François Duhem, Fabrice Muller, Robin Bonamy, and Sébastien Bilavarn, “FoRTReSS: a flow for design space exploration of partially reconfigurable systems,” Design Automation for Embedded Systems, 2015. View at Publisher · View at Google Scholar
  • V. Sakthivel, and Elizabeth Elias, “Design of low complexity sharp MDFT filter banks with perfect reconstruction using hybrid harmony-gravitational search algorithm,” Engineering Science and Technology, an International Journal, 2015. View at Publisher · View at Google Scholar
  • Jean-Philippe Diguet, Neil Bergmann, and Jean-Christophe Morgère, “Dedicated object processor for mobile augmented reality - sailor assistance case study,” EURASIP Journal on Embedded Systems, vol. 2015, no. 1, 2015. View at Publisher · View at Google Scholar
  • Runchun M. Wang, Tara J. Hamilton, Jonathan C. Tapson, and André van Schaik, “A neuromorphic implementation of multiple spike-timing synaptic plasticity rules for large-scale neural networks,” Frontiers in Neuroscience, vol. 9, 2015. View at Publisher · View at Google Scholar
  • Roberto Sierra, Carlos Carreras, Gabriel Caffarena, and Carlos A. Lopez Barrio, “A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors,” Ieee Transactions On Computer-Aided Design Of Integrated Circuits And Systems, vol. 34, no. 1, pp. 52–62, 2015. View at Publisher · View at Google Scholar
  • Mieczyslaw Jessa, “On the Quality of Random Sequences Produced with a Combined Random Bit Generator,” Ieee Transactions On Computers, vol. 64, no. 3, pp. 791–804, 2015. View at Publisher · View at Google Scholar
  • Honorio Martin, Thomas Korak, Enrique San Millan, and Michael Hutter, “Fault Attacks on STRNGs: Impact of Glitches, Temperature, and Underpowering on Randomness,” Ieee Transactions On Information Forensics And Security, vol. 10, no. 2, pp. 266–277, 2015. View at Publisher · View at Google Scholar
  • Bojan Jovanovic, Raphael M. Brum, and Lionel Torres, “Comparative Analysis of MTJ/CMOS Hybrid Cells Based on TAS and In-Plane STT Magnetic Tunnel Junctions,” Ieee Transactions On Magnetics, vol. 51, no. 2, 2015. View at Publisher · View at Google Scholar
  • Nuno Neves, Henrique Mendes, Ricardo Jorge Chaves, Pedro Tomas, and Nuno Roma, “Morphable hundred-core heterogeneous architecture for energy-aware computation,” Iet Computers And Digital Techniques, vol. 9, no. 1, pp. 49–62, 2015. View at Publisher · View at Google Scholar
  • Carlos A. Zerbini, and Jorge M. Finochietto, “Optimization of Lookup Schemes for Flow-Based Packet Classification on FPGAs,” International Journal of Reconfigurable Computing, vol. 2015, pp. 1–31, 2015. View at Publisher · View at Google Scholar
  • Jonas Gomes Filho, Marius Strum, and Wang Jiang Chau, “Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems,” International Journal of Reconfigurable Computing, vol. 2015, pp. 1–13, 2015. View at Publisher · View at Google Scholar
  • Ali Akbar Zarezadeh, Christophe Bobda, Franck Yonga, and Michael Mefenza, “Efficient network clustering for traffic reduction in embedded smart camera networks,” Journal of Real-Time Image Processing, 2015. View at Publisher · View at Google Scholar
  • Ricardo Ferreira, Waldir Denver, Monica Pereira, Stephan Wong, Carlos A. Lisbȏa, and Luigi Carro, “A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility,” Journal of Signal Processing Systems, 2015. View at Publisher · View at Google Scholar
  • Nehal N. Shah, and Upena D. Dalal, “Hardware Efficient Double Diamond Search Block Matching Algorithm for Fast Video Motion Estimation,” Journal of Signal Processing Systems, 2015. View at Publisher · View at Google Scholar
  • Arlindo R. Galvão Filho, Lauro C. Martins de Paula, Clarimar José Coelho, Telma Woerle de Lima, and Anderson da Silva Soares, “CUDA parallel programming for simulation of epidemiological models based on individuals,” Mathematical Methods in the Applied Sciences, 2015. View at Publisher · View at Google Scholar
  • Marcelo A. C. Fernandes, “Project-Based Learning Laboratory for Teaching Embedded Systems,” Mathematical Problems in Engineering, vol. 2015, pp. 1–8, 2015. View at Publisher · View at Google Scholar
  • Markus Weinhardt, Bernhard Lang, Frank M. Thiesing, Alexander Krieger, and Thomas Kinder, “SAccO: An Implementation Platform for Scalable FPGA Accelerators,” Microprocessors and Microsystems, 2015. View at Publisher · View at Google Scholar
  • Michael Bromberger, Fabian Nowak, and Wolfgang Karl, “Combined hardware-software multi-parallel prefiltering on the Convey HC-1 for fast homology detection,” Parallel Computing, vol. 42, pp. 4–17, 2015. View at Publisher · View at Google Scholar
  • Russell Tessier, Kenneth Pocek, and Andre DeHon, “Reconfigurable Computing Architectures,” Proceedings Of The Ieee, vol. 103, no. 3, pp. 332–354, 2015. View at Publisher · View at Google Scholar
  • Sparsh Mittal, and Jeffrey S. Vetter, “A Survey of Methods for Analyzing and Improving GPU Energy Efficiency,” ACM Computing Surveys, vol. 47, no. 2, pp. 1–23, 2014. View at Publisher · View at Google Scholar
  • Juan Antonio Clemente, Javier Resano, and Daniel Mozos, “An approach to manage reconfigurations and reduce area cost in hard real-time reconfigurable systems,” ACM Transactions on Embedded Computing Systems, vol. 13, no. 4, pp. 1–24, 2014. View at Publisher · View at Google Scholar
  • Parisa Razaghi, and Andreas Gerstlauer, “Host-Compiled Multicore System Simulation for Early Real-Time Performance Evaluation,” Acm Transactions On Embedded Computing Systems, vol. 13, 2014. View at Publisher · View at Google Scholar
  • Yuanwu Lei, Lei Guo, Yong Dou, Sheng Ma, and Jinbo Xu, “FPGA Implementation of a Special-Purpose VLIW Structure for Double-Precision Elementary Function,” Acm Transactions on Reconfigurable Technology and Systems, vol. 7, no. 2, 2014. View at Publisher · View at Google Scholar
  • Christian Brugger, Dominic Hillenbrand, and Matthias Balzer, “River,” ACM Transactions on Reconfigurable Technology and Systems, vol. 7, no. 3, pp. 1–16, 2014. View at Publisher · View at Google Scholar
  • Ihsan Cicek, Ali Emre Pusane, and Gunhan Dundar, “A new dual entropy core true random number generator,” Analog Integrated Circuits and Signal Processing, 2014. View at Publisher · View at Google Scholar
  • Benoit Larras, Bartosz Boguslawski, Cyril Lahuec, Matthieu Arzel, Fabrice Seguin, and Frédéric Heitzmann, “Analog encoded neural network for power management in MPSoC,” Analog Integrated Circuits and Signal Processing, 2014. View at Publisher · View at Google Scholar
  • Wen-Jyi Hwang, Hao-Tang Chan, and Chau-Jern Cheng, “Hologram authentication based on a secure watermarking algorithm using cellular automata,” Applied Optics, vol. 53, no. 27, pp. G64, 2014. View at Publisher · View at Google Scholar
  • Thomas Marconi, “Online scheduling and placement of hardware tasks with multiple variants on dynamically reconfigurable field-programmable gate arrays,” Computers & Electrical Engineering, vol. 40, no. 4, pp. 1215–1237, 2014. View at Publisher · View at Google Scholar
  • Romain Brillu, Sébastien Pillement, Fabrice Lemonnier, and Philippe Millet, “Cluster based MPSoC architecture: an on-chip message passing implementation,” Design Automation for Embedded Systems, 2014. View at Publisher · View at Google Scholar
  • Sang-Seol Lee, Sung-Joon Jang, Jungho Kim, Youngbae Hwang, and Byeongho Choi, “Memory-efficient SURF architecture for ASIC implementation,” Electronics Letters, vol. 50, no. 15, pp. 1059–1060, 2014. View at Publisher · View at Google Scholar
  • David E. Troncoso Romero, Uwe Meyer-Baese, and Gordana Jovanovic Dolecek, “On the inclusion of prime factors to calculate the theoretical lower bounds in multiplierless single constant multiplications,” Eurasip Journal on Advances in Signal Processing, 2014. View at Publisher · View at Google Scholar
  • Runchun M. Wang, Tara J. Hamilton, Jonathan C. Tapson, and André van Schaik, “A mixed-signal implementation of a polychronous spiking neural network with delay adaptation,” Frontiers in Neuroscience, vol. 8, 2014. View at Publisher · View at Google Scholar
  • Shu Y. Jiang, Gang Luo, Yue Liu, Shan S. Jiang, and Xiu T. Li, “Fault-Tolerant Routing Algorithm Simulation and Hardware Verification of NoC,” Ieee Transactions On Applied Superconductivity, vol. 24, no. 5, 2014. View at Publisher · View at Google Scholar
  • Juan Antonio Clemente, Elena Perez Ramo, Javier Resano, Daniel Mozos, and Francky Catthoor, “Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems,” Ieee Transactions on Very Large Scale Integration (vlsi) Systems, vol. 22, no. 6, pp. 1248–1261, 2014. View at Publisher · View at Google Scholar
  • Shuguo Li, “A Digital TRNG Based on Cross Feedback Ring Oscillators,” Ieice Transactions on Fundamentals of Electronics Communications and Comput, vol. E97A, no. 1, pp. 284–291, 2014. View at Publisher · View at Google Scholar
  • Hamad Marzouqi, Mahmoud Al-Qutayri, and Khaled Salah, “Review of gate-level differential power analysis and fault analysis countermeasures,” Iet Information Security, vol. 8, no. 1, pp. 51–66, 2014. View at Publisher · View at Google Scholar
  • Ihsan Cicek, Ali Emre Pusane, and Gunhan Dundar, “A novel design method for discrete time chaos based true random number generators,” Integration-The Vlsi Journal, vol. 47, no. 1, pp. 38–47, 2014. View at Publisher · View at Google Scholar
  • Mouna Ben Said, Yessine Hadj Kacem, Mickaël Kerboeuf, Nader Ben Amor, and Mohamed Abid, “Design Patterns for Self-Adaptive RTE Systems Specification,” International Journal of Reconfigurable Computing, vol. 2014, pp. 1–21, 2014. View at Publisher · View at Google Scholar
  • Tim Todman, Stephan Stilkerich, and Wayne Luk, “Using Statistical Assertions to Guide Self-Adaptive Systems,” International Journal of Reconfigurable Computing, vol. 2014, pp. 1–8, 2014. View at Publisher · View at Google Scholar
  • Mohsin Amin, Muhammad Shakir, Aqib Javed, Muhammad Hassan, and Syed Ali Raza, “Low-Cost Fault Tolerant Methodology for Real Time MPSoC Based Embedded System,” International Journal of Reconfigurable Computing, vol. 2014, pp. 1–8, 2014. View at Publisher · View at Google Scholar
  • Mouna Baklouti, and Mohamed Abid, “Multi-Softcore Architecture on FPGA,” International Journal of Reconfigurable Computing, vol. 2014, pp. 1–13, 2014. View at Publisher · View at Google Scholar
  • B. Jovanović, R. M. Brum, and L. Torres, “A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design,” Journal of Applied Physics, vol. 115, no. 13, pp. 134316, 2014. View at Publisher · View at Google Scholar
  • Naveed Imran, Rizwan A. Ashraf, Jooheung Lee, and Ronald F. DeMara, “Activity-Based Resource Allocation for Motion Estimation Engines,” Journal of Circuits, Systems and Computers, pp. 1550004, 2014. View at Publisher · View at Google Scholar
  • Meng Yang, Jinmei Lai, and A. E.A. Almaini, “An Architecture Independent Packing Method for LUT-based Commercial FPGA,” Journal of Computers, vol. 9, no. 5, 2014. View at Publisher · View at Google Scholar
  • Rajesh Kumar Pal, Kolin Paul, and Sanjiva Prasad, “ReKonf: Dynamically reconfigurable multiCore architecture,” Journal of Parallel and Distributed Computing, vol. 74, no. 11, pp. 3071–3086, 2014. View at Publisher · View at Google Scholar
  • Wei Guo, Guillaume Prenat, and Bernard Dieny, “A novel architecture of non-volatile magnetic arithmetic logic unit using magnetic tunnel junctions,” Journal of Physics D: Applied Physics, vol. 47, no. 16, pp. 165001, 2014. View at Publisher · View at Google Scholar
  • Xiaofang Wang, “Hardware-software optimizations of reconfigurable multi-core processors for floating-point computations of large sparse matrices,” Journal of Real-Time Image Processing, vol. 9, no. 1, pp. 187–204, 2014. View at Publisher · View at Google Scholar
  • Dario Socci, and Nicola Mazzocca, “ASP-based optimized mapping in a simulink-to-MPSoC design flow,” Journal of Systems Architecture, vol. 60, no. 1, pp. 108–118, 2014. View at Publisher · View at Google Scholar
  • Ismail San, and Nuray At, “Improving the computational efficiency of modular operations for embedded systems,” Journal of Systems Architecture, vol. 60, no. 5, pp. 440–451, 2014. View at Publisher · View at Google Scholar
  • Robert Brumnik, Vladislav Kovtun, Andrew Okhrimenko, and Sergii Kavun, “Techniques for Performance Improvement of Integer Multiplication in Cryptographic Applications,” Mathematical Problems in Engineering, vol. 2014, pp. 1–7, 2014. View at Publisher · View at Google Scholar
  • Vinod Pangracious, Emna Amouri, Zied Marakchi, and Habib Mehrez, “Architecture level optimization of 3-dimensional tree-based FPGA,” Microelectronics Journal, vol. 45, no. 4, pp. 355–366, 2014. View at Publisher · View at Google Scholar
  • Ludovic Devaux, and Sebastien Pillement, “OCEAN, a flexible adaptive Network-On-Chip for dynamic applications,” Microprocessors and Microsystems, 2014. View at Publisher · View at Google Scholar
  • Shweta Jain-Mendon, and Ron Sass, “A hardware–software co-design approach for implementing sparse matrix vector multiplication on FPGAs,” Microprocessors and Microsystems, 2014. View at Publisher · View at Google Scholar
  • Loïc Lagadec, Ciprian Teodorov, Jean-Christophe Le Lann, Damien Picard, and Erwan Fabiani, “Model-driven Toolset for Embedded Reconfigurable Cores: Flexible Prototyping and Software-like Debugging,” Science of Computer Programming, 2014. View at Publisher · View at Google Scholar
  • Charalampos Manifavas, Konstantinos Fysarakis, Alexandros Papanikolaou, and Ioannis Papaefstathiou, “Embedded Systems Security: A Survey of EU Research Efforts,” Security and Communication Networks, 2014. View at Publisher · View at Google Scholar
  • H. Daryanavard, M. Eshghi, and A. Jahanian, “A fast placement algorithm for embedded just-in-time reconfigurable extensible processing platform,” The Journal of Supercomputing, 2014. View at Publisher · View at Google Scholar
  • Daniel Llamocca, and Marios Pattichis, “A Self-Reconfigurable Platform for the Implementation of 2D Filterbanks with Real and Complex-Valued Inputs, Outputs, and Filter Coefficients,” VLSI Design, vol. 2014, pp. 1–24, 2014. View at Publisher · View at Google Scholar
  • Javier Hormigo, Juan P. Oliver, and Eduardo Boemo, “Self-Reconfigurable Constant Multiplier for FPGA,” Acm Transactions on Reconfigurable Technology and Systems, vol. 6, no. 3, 2013. View at Publisher · View at Google Scholar
  • Chun-Hsian Huang, and Pao-Ann Hsiung, “Virtualizable Hardware/Software Design Infrastructure for Dynamically Partially Reconfigurable Systems,” Acm Transactions On Reconfigurable Technology And Systems, vol. 6, no. 2, 2013. View at Publisher · View at Google Scholar
  • Hanyu Liu, Senthilkumar T. Rajavel, and Ali Akoglu, “Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms,” Acm Transactions on Reconfigurable Technology and Systems, vol. 6, no. 3, 2013. View at Publisher · View at Google Scholar
  • Yamuna Rajasekhar, and Ron Sass, “Architecture and applications for an All-FPGA parallel computer,” Cluster Computing, 2013. View at Publisher · View at Google Scholar
  • Karol Gugala, Aleksandra Swietlicka, Michal Burdajewicz, and Andrzej Rybarczyk, “Random number generation system improving simulations of stochastic models of neural cells,” Computing, vol. 95, no. 1, pp. S259–S275, 2013. View at Publisher · View at Google Scholar
  • E. Ostua, J. Juan, M. J. Bellido, J. Viejo, and D. Guerrero, “NanoFS: a hardware-oriented file system,” Electronics Letters, vol. 49, no. 19, 2013. View at Publisher · View at Google Scholar
  • Konrad Moeller, Uwe Meyer-Baese, Martin Kumm, Diana Fanghaenel, and Peter Zipf, “FIR filter optimization for video processing on FPGAs,” Eurasip Journal On Advances In Signal Processing, 2013. View at Publisher · View at Google Scholar
  • Daniel Llamocca, and Marios Pattichis, “A Dynamically Reconfigurable Pixel Processor System Based on Power/Energy-Performance-Accuracy Optimization,” Ieee Transactions On Circuits And Systems For Video Technology, vol. 23, no. 3, pp. 488–502, 2013. View at Publisher · View at Google Scholar
  • Chang-Hsiung Tsai, “A Quick Pessimistic Diagnosis Algorithm for Hypercube-Like Multiprocessor Systems under the PMC Model,” Ieee Transactions On Computers, vol. 62, no. 2, pp. 259–267, 2013. View at Publisher · View at Google Scholar
  • Louis-Marie Aubert, Richard Veitch, Scott Fischaber, and Roger Woods, “Optimization of Weighted Finite State Transducer for Speech Recognition,” Ieee Transactions On Computers, vol. 62, no. 8, pp. 1607–1615, 2013. View at Publisher · View at Google Scholar
  • Rizwan A. Ashraf, and Ronald F. Demara, “Scalable FPGA refurbishment using netlist-driven evolutionary algorithms,” IEEE Transactions on Computers, vol. 62, no. 8, pp. 1526–1541, 2013. View at Publisher · View at Google Scholar
  • Xabier Iturbe, Chuan Hong, Raul Torrego, Imanol Martinez, Tughrul Arslan, Jon Perez, Khaled Benkrid, and Ali Ebrahim, “R3TOS: A Novel Reliable Reconfigurable Real-Time Operating System for Highly Adaptive, Efficient, and Dependable Computing on FPGAs,” Ieee Transactions On Computers, vol. 62, no. 8, pp. 1542–1556, 2013. View at Publisher · View at Google Scholar
  • Rabie Ben Atitallah, Eric Senn, Daniel Chillet, Mickael Lanoe, and Dominique Blouin, “An Efficient Framework for Power-Aware Design of Heterogeneous MPSoC,” Ieee Transactions On Industrial Informatics, vol. 9, no. 1, pp. 487–501, 2013. View at Publisher · View at Google Scholar
  • Heather M. Quinn, Dolores A. Black, Stephen P. Buchner, and William H. Robinson, “Fault Simulation and Emulation Tools to Augment Radiation-Hardness Assurance Testing,” Ieee Transactions On Nuclear Science, vol. 60, no. 3, pp. 2119–2142, 2013. View at Publisher · View at Google Scholar
  • G. Drake, W. S. Fernando, and R. W. Stanek, “Modulator-Based, High Bandwidth Optical Links for HEP Experiments,” Ieee Transactions on Nuclear Science, vol. 60, no. 5, pp. 3497–3501, 2013. View at Publisher · View at Google Scholar
  • Snaider Carrillo, Jim Harkin, Liam J. McDaid, Fearghal Morgan, Sandeep Pande, Seamus Cawley, and Brian McGinley, “Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations,” Ieee Transactions on Parallel and Distributed Systems, vol. 24, no. 12, pp. 2451–2461, 2013. View at Publisher · View at Google Scholar
  • Dajiang Liu, Shaojun Wei, Shouyi Yin, and Leibo Liu, “Affine Transformations for Communication and Reconfiguration Optimization of Mapping Loop Nests on CGRAs,” Ieice Transactions On Information And Systems, vol. E96D, no. 8, pp. 1582–1591, 2013. View at Publisher · View at Google Scholar
  • Wei Chen, and Richard P. Mied, “Optical flow estimation for motion-compensated compression,” Image and Vision Computing, vol. 31, no. 3, pp. 275–289, 2013. View at Publisher · View at Google Scholar
  • Pedrino, Roda, Kato, Saito, Tronco, Tsunaki, Morandin Jr., and Nicoletti, “A genetic programming based system for the automatic construction of image filters,” Integrated Computer-Aided Engineering, vol. 20, no. 3, pp. 275–287, 2013. View at Publisher · View at Google Scholar
  • Placido Rogerio Pinheiro, Álvaro Meneses Sobreira Neto, and Alexei Barbosa Aguiar, “Handing Optimization Energy Consumption in Heterogeneous Wireless Sensor Networks,” International Journal of Distributed Sensor Networks, vol. 2013, pp. 1–9, 2013. View at Publisher · View at Google Scholar
  • O. Ahmed, S. Areibi, R. Collier, and G. Grewal, “An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization,” International Journal of Reconfigurable Computing, vol. 2013, pp. 1–23, 2013. View at Publisher · View at Google Scholar
  • Malte Baesler, and Sven-Ole Voigt, “Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs,” International Journal of Reconfigurable Computing, vol. 2013, pp. 1–16, 2013. View at Publisher · View at Google Scholar
  • Ahmed, Areibi, and Grewal, “Hardware accelerators targeting a novel group based packet classification algorithm,” International Journal of Reconfigurable Computing, vol. 2013, 2013. View at Publisher · View at Google Scholar
  • Krzysztof Jozwik, Shinya Honda, Masato Edahiro, Hiroyuki Tomiyama, and Hiroaki Takada, “Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs,” International Journal of Reconfigurable Computing, vol. 2013, pp. 1–40, 2013. View at Publisher · View at Google Scholar
  • Chuan Hong, Ali Ebrahim, Tughrul Arslan, Imanol Martinez, Xabier Iturbe, and Khaled Benkrid, “Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence,” International Journal of Reconfigurable Computing, vol. 2013, pp. 1–32, 2013. View at Publisher · View at Google Scholar
  • Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang, and Jinian Bian, “Unification Of Pr Region Floorplanning And Fine-Grained Placement For Dynamic Partially Reconfigurable Fpgas,” Journal Of Circuits Systems And Computers, vol. 22, no. 4, 2013. View at Publisher · View at Google Scholar
  • Costas E. Goutis, George Theodoridis, George S. Athanasiou, Harris E. Michail, and Takis Kasparis, “A Systematic Flow For Developing Totally Self-Checking Architectures For Sha-1 And Sha-2 Cryptographic Hash Families,” Journal Of Circuits Systems And Computers, vol. 22, no. 6, 2013. View at Publisher · View at Google Scholar
  • Bouraoui Ouni, and Abdellatif Mtibaa, “Online scheduling and placement of hardware modules on partially dynamic architectures,” Journal of Circuits, Systems and Computers, vol. 22, no. 3, 2013. View at Publisher · View at Google Scholar
  • Yanqin Bai, and Chuanhao Guo, “Doubly nonnegative relaxation method for solving multiple objective quadratic programming problems,” Journal of Industrial and Management Optimization, vol. 10, no. 2, pp. 543–556, 2013. View at Publisher · View at Google Scholar
  • Shih-An Li, Ching-Yi Chen, and Ching-Han Chen, “Design of a shift-and-add based hardware accelerator for color space conversion,” Journal of Real-Time Image Processing, 2013. View at Publisher · View at Google Scholar
  • Sol Pedre, Tomáš Krajník, Elías Todorovich, and Patricia Borensztejn, “Accelerating embedded image processing for real time: a case study,” Journal of Real-Time Image Processing, 2013. View at Publisher · View at Google Scholar
  • Yusuf Aksehir, Kamil Erdayandi, Tevfik Zafer Ozcan, and Ilker Hamzaoglu, “A low energy adaptive motion estimation hardware for H.264 multiview video coding,” Journal of Real-Time Image Processing, 2013. View at Publisher · View at Google Scholar
  • Rafael Ramos-Lara, Mariano Lopez-Garcia, Enrique Canto-Navarro, and Luis Puente-Rodriguez, “Real-Time Speaker Verification System Implemented on Reconfigurable Hardware,” Journal Of Signal Processing Systems For Signal Image And Video Technology, vol. 71, no. 2, pp. 89–103, 2013. View at Publisher · View at Google Scholar
  • Alexandra Aguiar, Sergio Johann Filho, Felipe Magalhaes, and Fabiano Hessel, “On the design space exploration through the Hellfire Framework,” Journal of Systems Architecture, 2013. View at Publisher · View at Google Scholar