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Citations to this Journal [181 citations: 1–100 of 163 articles]

Articles published in International Journal of Reconfigurable Computing have been cited 181 times. The following is a list of the 163 articles that have cited the articles published in International Journal of Reconfigurable Computing.

  • Yuanwu Lei, Lei Guo, Yong Dou, Sheng Ma, and Jinbo Xu, “FPGA Implementation of a Special-Purpose VLIW Structure for Double-Precision Elementary Function,” Acm Transactions on Reconfigurable Technology and Systems, vol. 7, no. 2, 2014. View at Publisher · View at Google Scholar
  • Ihsan Cicek, Ali Emre Pusane, and Gunhan Dundar, “A new dual entropy core true random number generator,” Analog Integrated Circuits and Signal Processing, 2014. View at Publisher · View at Google Scholar
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  • Shuguo Li, “A Digital TRNG Based on Cross Feedback Ring Oscillators,” Ieice Transactions on Fundamentals of Electronics Communications and Comput, vol. E97A, no. 1, pp. 284–291, 2014. View at Publisher · View at Google Scholar
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  • Mouna Ben Said, Yessine Hadj Kacem, Mickaël Kerboeuf, Nader Ben Amor, and Mohamed Abid, “Design Patterns for Self-Adaptive RTE Systems Specification,” International Journal of Reconfigurable Computing, vol. 2014, pp. 1–21, 2014. View at Publisher · View at Google Scholar
  • Tim Todman, Stephan Stilkerich, and Wayne Luk, “Using Statistical Assertions to Guide Self-Adaptive Systems,” International Journal of Reconfigurable Computing, vol. 2014, pp. 1–8, 2014. View at Publisher · View at Google Scholar
  • B. Jovanović, R. M. Brum, and L. Torres, “A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design,” Journal of Applied Physics, vol. 115, no. 13, pp. 134316, 2014. View at Publisher · View at Google Scholar
  • Naveed Imran, Rizwan A. Ashraf, Jooheung Lee, and Ronald F. DeMara, “Activity-Based Resource Allocation for Motion Estimation Engines,” Journal of Circuits, Systems and Computers, pp. 1550004, 2014. View at Publisher · View at Google Scholar
  • Meng Yang, Jinmei Lai, and A. E.A. Almaini, “An Architecture Independent Packing Method for LUT-based Commercial FPGA,” Journal of Computers, vol. 9, no. 5, 2014. View at Publisher · View at Google Scholar
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  • Xiaofang Wang, “Hardware-software optimizations of reconfigurable multi-core processors for floating-point computations of large sparse matrices,” Journal of Real-Time Image Processing, vol. 9, no. 1, pp. 187–204, 2014. View at Publisher · View at Google Scholar
  • Dario Socci, and Nicola Mazzocca, “ASP-based optimized mapping in a simulink-to-MPSoC design flow,” Journal of Systems Architecture, vol. 60, no. 1, pp. 108–118, 2014. View at Publisher · View at Google Scholar
  • Ismail San, and Nuray At, “Improving the computational efficiency of modular operations for embedded systems,” Journal of Systems Architecture, vol. 60, no. 5, pp. 440–451, 2014. View at Publisher · View at Google Scholar
  • Robert Brumnik, Vladislav Kovtun, Andrew Okhrimenko, and Sergii Kavun, “Techniques for Performance Improvement of Integer Multiplication in Cryptographic Applications,” Mathematical Problems in Engineering, vol. 2014, pp. 1–7, 2014. View at Publisher · View at Google Scholar
  • Vinod Pangracious, Emna Amouri, Zied Marakchi, and Habib Mehrez, “Architecture level optimization of 3-dimensional tree-based FPGA,” Microelectronics Journal, vol. 45, no. 4, pp. 355–366, 2014. View at Publisher · View at Google Scholar
  • Ludovic Devaux, and Sebastien Pillement, “OCEAN, a flexible adaptive Network-On-Chip for dynamic applications,” Microprocessors and Microsystems, 2014. View at Publisher · View at Google Scholar
  • Shweta Jain-Mendon, and Ron Sass, “A hardware–software co-design approach for implementing sparse matrix vector multiplication on FPGAs,” Microprocessors and Microsystems, 2014. View at Publisher · View at Google Scholar
  • Loïc Lagadec, Ciprian Teodorov, Jean-Christophe Le Lann, Damien Picard, and Erwan Fabiani, “Model-driven Toolset for Embedded Reconfigurable Cores: Flexible Prototyping and Software-like Debugging,” Science of Computer Programming, 2014. View at Publisher · View at Google Scholar
  • H. Daryanavard, M. Eshghi, and A. Jahanian, “A fast placement algorithm for embedded just-in-time reconfigurable extensible processing platform,” The Journal of Supercomputing, 2014. View at Publisher · View at Google Scholar
  • Daniel Llamocca, and Marios Pattichis, “A Self-Reconfigurable Platform for the Implementation of 2D Filterbanks with Real and Complex-Valued Inputs, Outputs, and Filter Coefficients,” VLSI Design, vol. 2014, pp. 1–24, 2014. View at Publisher · View at Google Scholar
  • Javier Hormigo, Juan P. Oliver, and Eduardo Boemo, “Self-Reconfigurable Constant Multiplier for FPGA,” Acm Transactions on Reconfigurable Technology and Systems, vol. 6, no. 3, 2013. View at Publisher · View at Google Scholar
  • Chun-Hsian Huang, and Pao-Ann Hsiung, “Virtualizable Hardware/Software Design Infrastructure for Dynamically Partially Reconfigurable Systems,” Acm Transactions On Reconfigurable Technology And Systems, vol. 6, no. 2, 2013. View at Publisher · View at Google Scholar
  • Hanyu Liu, Senthilkumar T. Rajavel, and Ali Akoglu, “Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms,” Acm Transactions on Reconfigurable Technology and Systems, vol. 6, no. 3, 2013. View at Publisher · View at Google Scholar
  • Yamuna Rajasekhar, and Ron Sass, “Architecture and applications for an All-FPGA parallel computer,” Cluster Computing, 2013. View at Publisher · View at Google Scholar
  • Karol Gugala, Aleksandra Swietlicka, Michal Burdajewicz, and Andrzej Rybarczyk, “Random number generation system improving simulations of stochastic models of neural cells,” Computing, vol. 95, no. 1, pp. S259–S275, 2013. View at Publisher · View at Google Scholar
  • E. Ostua, J. Juan, M. J. Bellido, J. Viejo, and D. Guerrero, “NanoFS: a hardware-oriented file system,” Electronics Letters, vol. 49, no. 19, 2013. View at Publisher · View at Google Scholar
  • Konrad Moeller, Uwe Meyer-Baese, Martin Kumm, Diana Fanghaenel, and Peter Zipf, “FIR filter optimization for video processing on FPGAs,” Eurasip Journal On Advances In Signal Processing, 2013. View at Publisher · View at Google Scholar
  • Daniel Llamocca, and Marios Pattichis, “A Dynamically Reconfigurable Pixel Processor System Based on Power/Energy-Performance-Accuracy Optimization,” Ieee Transactions On Circuits And Systems For Video Technology, vol. 23, no. 3, pp. 488–502, 2013. View at Publisher · View at Google Scholar
  • Chang-Hsiung Tsai, “A Quick Pessimistic Diagnosis Algorithm for Hypercube-Like Multiprocessor Systems under the PMC Model,” Ieee Transactions On Computers, vol. 62, no. 2, pp. 259–267, 2013. View at Publisher · View at Google Scholar
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  • Xabier Iturbe, Chuan Hong, Raul Torrego, Imanol Martinez, Tughrul Arslan, Jon Perez, Khaled Benkrid, and Ali Ebrahim, “R3TOS: A Novel Reliable Reconfigurable Real-Time Operating System for Highly Adaptive, Efficient, and Dependable Computing on FPGAs,” Ieee Transactions On Computers, vol. 62, no. 8, pp. 1542–1556, 2013. View at Publisher · View at Google Scholar
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  • Heather M. Quinn, Dolores A. Black, Stephen P. Buchner, and William H. Robinson, “Fault Simulation and Emulation Tools to Augment Radiation-Hardness Assurance Testing,” Ieee Transactions On Nuclear Science, vol. 60, no. 3, pp. 2119–2142, 2013. View at Publisher · View at Google Scholar
  • G. Drake, W. S. Fernando, and R. W. Stanek, “Modulator-Based, High Bandwidth Optical Links for HEP Experiments,” Ieee Transactions on Nuclear Science, vol. 60, no. 5, pp. 3497–3501, 2013. View at Publisher · View at Google Scholar
  • Snaider Carrillo, Jim Harkin, Liam J. McDaid, Fearghal Morgan, Sandeep Pande, Seamus Cawley, and Brian McGinley, “Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations,” Ieee Transactions on Parallel and Distributed Systems, vol. 24, no. 12, pp. 2451–2461, 2013. View at Publisher · View at Google Scholar
  • Dajiang Liu, Shaojun Wei, Shouyi Yin, and Leibo Liu, “Affine Transformations for Communication and Reconfiguration Optimization of Mapping Loop Nests on CGRAs,” Ieice Transactions On Information And Systems, vol. E96D, no. 8, pp. 1582–1591, 2013. View at Publisher · View at Google Scholar
  • Wei Chen, and Richard P. Mied, “Optical flow estimation for motion-compensated compression,” Image and Vision Computing, vol. 31, no. 3, pp. 275–289, 2013. View at Publisher · View at Google Scholar
  • Pedrino, Roda, Kato, Saito, Tronco, Tsunaki, Morandin Jr., and Nicoletti, “A genetic programming based system for the automatic construction of image filters,” Integrated Computer-Aided Engineering, vol. 20, no. 3, pp. 275–287, 2013. View at Publisher · View at Google Scholar
  • Placido Rogerio Pinheiro, Álvaro Meneses Sobreira Neto, and Alexei Barbosa Aguiar, “Handing Optimization Energy Consumption in Heterogeneous Wireless Sensor Networks,” International Journal of Distributed Sensor Networks, vol. 2013, pp. 1–9, 2013. View at Publisher · View at Google Scholar
  • O. Ahmed, S. Areibi, R. Collier, and G. Grewal, “An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization,” International Journal of Reconfigurable Computing, vol. 2013, pp. 1–23, 2013. View at Publisher · View at Google Scholar
  • Malte Baesler, and Sven-Ole Voigt, “Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs,” International Journal of Reconfigurable Computing, vol. 2013, pp. 1–16, 2013. View at Publisher · View at Google Scholar
  • Ahmed, Areibi, and Grewal, “Hardware accelerators targeting a novel group based packet classification algorithm,” International Journal of Reconfigurable Computing, vol. 2013, 2013. View at Publisher · View at Google Scholar
  • Krzysztof Jozwik, Shinya Honda, Masato Edahiro, Hiroyuki Tomiyama, and Hiroaki Takada, “Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs,” International Journal of Reconfigurable Computing, vol. 2013, pp. 1–40, 2013. View at Publisher · View at Google Scholar
  • Chuan Hong, Ali Ebrahim, Tughrul Arslan, Imanol Martinez, Xabier Iturbe, and Khaled Benkrid, “Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence,” International Journal of Reconfigurable Computing, vol. 2013, pp. 1–32, 2013. View at Publisher · View at Google Scholar
  • Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang, and Jinian Bian, “Unification Of Pr Region Floorplanning And Fine-Grained Placement For Dynamic Partially Reconfigurable Fpgas,” Journal Of Circuits Systems And Computers, vol. 22, no. 4, 2013. View at Publisher · View at Google Scholar
  • Costas E. Goutis, George Theodoridis, George S. Athanasiou, Harris E. Michail, and Takis Kasparis, “A Systematic Flow For Developing Totally Self-Checking Architectures For Sha-1 And Sha-2 Cryptographic Hash Families,” Journal Of Circuits Systems And Computers, vol. 22, no. 6, 2013. View at Publisher · View at Google Scholar
  • Bouraoui Ouni, and Abdellatif Mtibaa, “Online scheduling and placement of hardware modules on partially dynamic architectures,” Journal of Circuits, Systems and Computers, vol. 22, no. 3, 2013. View at Publisher · View at Google Scholar
  • Yanqin Bai, and Chuanhao Guo, “Doubly nonnegative relaxation method for solving multiple objective quadratic programming problems,” Journal of Industrial and Management Optimization, vol. 10, no. 2, pp. 543–556, 2013. View at Publisher · View at Google Scholar
  • Shih-An Li, Ching-Yi Chen, and Ching-Han Chen, “Design of a shift-and-add based hardware accelerator for color space conversion,” Journal of Real-Time Image Processing, 2013. View at Publisher · View at Google Scholar
  • Sol Pedre, Tomáš Krajník, Elías Todorovich, and Patricia Borensztejn, “Accelerating embedded image processing for real time: a case study,” Journal of Real-Time Image Processing, 2013. View at Publisher · View at Google Scholar
  • Yusuf Aksehir, Kamil Erdayandi, Tevfik Zafer Ozcan, and Ilker Hamzaoglu, “A low energy adaptive motion estimation hardware for H.264 multiview video coding,” Journal of Real-Time Image Processing, 2013. View at Publisher · View at Google Scholar
  • Rafael Ramos-Lara, Mariano Lopez-Garcia, Enrique Canto-Navarro, and Luis Puente-Rodriguez, “Real-Time Speaker Verification System Implemented on Reconfigurable Hardware,” Journal Of Signal Processing Systems For Signal Image And Video Technology, vol. 71, no. 2, pp. 89–103, 2013. View at Publisher · View at Google Scholar
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