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Citations to this Journal [185 citations: 101–167 of 167 articles]

Articles published in International Journal of Reconfigurable Computing have been cited 185 times. The following is a list of the 167 articles that have cited the articles published in International Journal of Reconfigurable Computing.

  • Kaveh Aasaraai, and Andreas Moshovos, “NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution,” International Journal of Reconfigurable Computing, vol. 2012, pp. 1–12, 2012. View at Publisher · View at Google Scholar
  • Yi Zhan, and Tadahiro Kuroda, “Wearable sensor-based human activity recognition from environmental background sounds,” Journal of Ambient Intelligence and Humanized Computing, 2012. View at Publisher · View at Google Scholar
  • Yousri Ouerhani, Maher Jridi, and Ayman Alfalou, “Area-Delay Efficient Fft Architecture Using Parallel Processing And New Memory Sharing Technique,” Journal Of Circuits Systems And Computers, vol. 21, no. 6, 2012. View at Publisher · View at Google Scholar
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  • John A. Kalomiros, “Dense disparity features for fast stereo vision,” Journal of Electronic Imaging, vol. 21, no. 4, 2012. View at Publisher · View at Google Scholar
  • Sardar Anisul Haque, and Marc Moreno Maza, “Plain polynomial arithmetic on GPU,” Journal of Physics: Conference Series, vol. 385, no. 1, 2012. View at Publisher · View at Google Scholar
  • Matthias Birk, Michael Zapf, Matthias Balzer, Nicole Ruiter, and Jürgen Becker, “A comprehensive comparison of GPU- and FPGA-based acceleration of reflection image reconstruction for 3D ultrasound computer tomography,” Journal of Real-Time Image Processing, vol. 9, no. 1, pp. 159–170, 2012. View at Publisher · View at Google Scholar
  • Pierre-Henri Horrein, Christine Hennebert, and Frédéric Pétrot, “An environment for (re)configuration and execution management of heterogeneous flexible radio platforms,” Microprocessors and Microsystems, 2012. View at Publisher · View at Google Scholar
  • Snaider Carrillo, Jim Harkin, Liam McDaid, Sandeep Pande, Seamus Cawley, Brian McGinley, and Fearghal Morgan, “Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers,” Neural Networks, vol. 33, pp. 42–57, 2012. View at Publisher · View at Google Scholar
  • Andrew G. Schmidt, Siddhartha Datta, Ashwin A. Mendon, and Ron Sass, “Investigation into scaling I/O bound streaming applications productively with an all-FPGA cluster,” Parallel Computing, vol. 38, no. 8, pp. 344–364, 2012. View at Publisher · View at Google Scholar
  • Emanuele Cannella, Onur Derin, Paolo Meloni, Giuseppe Tuveri, and Todor Stefanov, “Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks,” VLSI Design, vol. 2012, pp. 1–17, 2012. View at Publisher · View at Google Scholar
  • Emanuele Cannella, Lorenzo Di Gregorio, Leandro Fiorin, Menno Lindwer, Paolo Melonr, Olaf Neugebauer, and Andy Pimentel, “Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?,” 2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2011, pp. 120–129, 2011. View at Publisher · View at Google Scholar
  • Ekaterina Gonina, Gerald Friedland, Henry Cook, and Kurt Keutzer, “Fast speaker diarization using a high-level scripting language,” 2011 IEEE Workshop on Automatic Speech Recognition and Understanding, ASRU 2011, Proceedings, pp. 553–558, 2011. View at Publisher · View at Google Scholar
  • Ikbel Belaid, Fabrice Muller, and Maher Benjemaa, “Optimal static scheduling of real-time dependent tasks on reconfigurable hardware devices,” 2011 International Conference on Communications, Computing and Control Applications, CCCA 2011, 2011. View at Publisher · View at Google Scholar
  • Martin Kumm, and Peter Zipf, “High speed low complexity FPGA-based FIR filters using pipelined adder graphs,” 2011 International Conference on Field-Programmable Technology, FPT 2011, 2011. View at Publisher · View at Google Scholar
  • Gian Carlo Cardarilli, Marco Re, Ilir Shuli, and Lorenzo Simone, “Partial reconfiguration in the implementation of autonomous radio receivers for space,” 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2011 - Proceedings, 2011. View at Publisher · View at Google Scholar
  • Hung-Manh Pham, Ludovic Devaux, and Sébastien Pillement, “Re2DA: Reliable and reconfigurable dynamic architecture,” 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2011 - Proceedings, 2011. View at Publisher · View at Google Scholar
  • Scott Lloyd, and Quinn O. Snell, “Accelerated large-scale multiple sequence alignment,” Bmc Bioinformatics, vol. 12, 2011. View at Publisher · View at Google Scholar
  • Noor Elaiza Abdul Khalid, Norharyati Md Ariff, Saadiah Yahya, and Noorhayati Mohamed Noor, “A review of bio-inspired algorithms as image processing techniques,” Communications in Computer and Information Science, vol. 179, no. 1, pp. 660–673, 2011. View at Publisher · View at Google Scholar
  • Matthias Birk, Alexander Guth, Michael Zapf, Matthias Balzer, Nicole Ruiter, Michael Hübner, and Jürgen Becker, “Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing,” Conference on Design and Architectures for Signal and Image Processing, DASIP, pp. 67–74, 2011. View at Publisher · View at Google Scholar
  • Emanuele Cannella, Onur Derin, and Todor Stefanov, “Middleware approaches for adaptivity of Kahn process networks on networks-on-chip,” Conference on Design and Architectures for Signal and Image Processing, DASIP, pp. 100–107, 2011. View at Publisher · View at Google Scholar
  • Bertrand Le Gal, and Emmanuel Casseau, “Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design,” Eurasip Journal on Advances in Signal Processing, 2011. View at Publisher · View at Google Scholar
  • Ruben Salvador, Felix Moreno, Teresa Riesgo, and Lukas Sekanina, “Evolutionary Approach to Improve Wavelet Transforms for Image Compression in Embedded Systems,” Eurasip Journal On Advances In Signal Processing, 2011. View at Publisher · View at Google Scholar
  • Seamus Cawley, Fearghal Morgan, Brian McGinley, Sandeep Pande, Liam McDaid, Snaider Carrillo, and Jim Harkin, “Hardware spiking neural network prototyping and application,” Genetic Programming and Evolvable Machines, vol. 12, no. 3, pp. 257–280, 2011. View at Publisher · View at Google Scholar
  • Mehdi Alipour, Mostafa E. Salehi, and Kamran Moshari, “Cache power and performance tradeoffs for embedded applications,” ICCAIE 2011 - 2011 IEEE Conference on Computer Applications and Industrial Electronics, pp. 26–31, 2011. View at Publisher · View at Google Scholar
  • Richard Veitch, Roger Woods, and Louis-Marie Aubert, “GPU acceleration of automated speech recognition for mobile devices,” IEEE International Conference on Industrial Informatics (INDIN), pp. 823–828, 2011. View at Publisher · View at Google Scholar
  • Alexander Wold, Dirk Koch, and Jim Torresen, “Enhancing resource utilization with design alternatives in runtime reconfigurable systems,” IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, pp. 264–270, 2011. View at Publisher · View at Google Scholar
  • Greg Stitt, “Are field-programmable gate arrays ready for the mainstream?,” IEEE Micro, vol. 31, no. 6, pp. 58–63, 2011. View at Publisher · View at Google Scholar
  • Chun-Hsian Huang, and Pao-Ann Hsiung, “Model-Based Verification and Estimation Framework for Dynamically Partially Reconfigurable Systems,” Ieee Transactions On Industrial Informatics, vol. 7, no. 2, pp. 287–301, 2011. View at Publisher · View at Google Scholar
  • Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, and Toshinori Sueyoshi, “A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells,” Ieice Transactions on Electronics, vol. E94C, no. 4, pp. 548–556, 2011. View at Publisher · View at Google Scholar
  • C. Desmouliers, E. Oruklu, and J. Saniie, “Discrete wavelet transform realisation using run-time reconfiguration of field programmable gate array (FPGA)s,” IET Circuits, Devices & Systems, vol. 5, no. 4, pp. 321, 2011. View at Publisher · View at Google Scholar
  • Marcel M. Corrêa, Mateus T. Schoenknecht, Robson S. Dornelles, and Luciano V. Agostini, “A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos,” International Journal of Reconfigurable Computing, vol. 2011, pp. 1–9, 2011. View at Publisher · View at Google Scholar
  • John C. Hoffman, and Marios S. Pattichis, “A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback,” International Journal of Reconfigurable Computing, vol. 2011, pp. 1–10, 2011. View at Publisher · View at Google Scholar
  • Stefan Döbrich, and Christian Hochberger, “Exploring Online Synthesis for CGRAs with Specialized Operator Sets,” International Journal of Reconfigurable Computing, vol. 2011, pp. 1–22, 2011. View at Publisher · View at Google Scholar
  • Brian Pratt, Megan Fuller, and Michael Wirthlin, “Reduced-Precision Redundancy on FPGAs,” International Journal of Reconfigurable Computing, vol. 2011, pp. 1–12, 2011. View at Publisher · View at Google Scholar
  • Loïc Lagadec, Damien Picard, Youenn Corre, and Pierre-Yves Lucas, “Experiment Centric Teaching for Reconfigurable Processors,” International Journal of Reconfigurable Computing, vol. 2011, pp. 1–14, 2011. View at Publisher · View at Google Scholar
  • Davide Anguita, Luca Carlino, Alessandro Ghio, and Sandro Ridella, “A Fpga Core Generator For Embedded Classification Systems,” Journal Of Circuits Systems And Computers, vol. 20, no. 2, pp. 263–282, 2011. View at Publisher · View at Google Scholar
  • Xuefeng Liang, Alan Johnston, and Peter W. McOwan, “Biologically inspired framework for spatial and spectral velocity estimations,” Journal Of The Optical Society Of America A-Optics Image Science And Vision, vol. 28, no. 4, pp. 713–723, 2011. View at Publisher · View at Google Scholar
  • Haiyun Gu, “A review of research on network-on-chip simulator,” Lecture Notes in Electrical Engineering, vol. 100, no. 4, pp. 103–110, 2011. View at Publisher · View at Google Scholar
  • Haiyun Gu, “Design methodology of dynamically reconfigurable network-on-chip,” Lecture Notes in Electrical Engineering, vol. 100, no. 4, pp. 111–116, 2011. View at Publisher · View at Google Scholar
  • N. Izeboudjen, A. Bouridane, A. Farah, and H. Bessalah, “Application of design reuse to artificial neural networks: case study of the back propagation algorithm,” Neural Computing and Applications, vol. 21, no. 7, pp. 1531–1544, 2011. View at Publisher · View at Google Scholar
  • Mehdi Alipour, Kamran Moshari, and Mohammad Reza Bagheri, “Performance per power optimum cache architecture for embedded applications, a design space exploration,” Proceedings - 2011 IEEE 2nd International Conference on Networked Embedded Systems for Enterprise Applications, NESEA 2011, 2011. View at Publisher · View at Google Scholar
  • Malte Baesler, Sven-Ole Voigt, and Thomas Teufel, “FPGA implementations of radix-10 digit recurrence fixed-point and floating-point dividers,” Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, pp. 13–19, 2011. View at Publisher · View at Google Scholar
  • Rajesh Velegalati, and Jens-Peter Kaps, “Improving security of SDDL designs through interleaved placement on Xilinx FPGAs,” Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011, pp. 506–511, 2011. View at Publisher · View at Google Scholar
  • Daniel Llamocca, Cesar Carranza, and Marios Pattichis, “Separable FIR filtering in FPGA and GPU implementations: Energy, performance, and accuracy considerations,” Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011, pp. 363–368, 2011. View at Publisher · View at Google Scholar
  • Monica Magalhães Pereira, Lars Braun, Michael Hübner, Jürgen Becker, and Luigi Carro, “Run-time resource instantiation for fault tolerance in FPGAs,” Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2011, pp. 88–95, 2011. View at Publisher · View at Google Scholar
  • John A. Kalomiros, “Dense disparity features for fast stereo vision,” Proceedings of the 6th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, IDAACS'2011, vol. 1, pp. 426–429, 2011. View at Publisher · View at Google Scholar
  • Umer Nisar Misgar, and Muhammad Hasan, “Performance analysis of different multiplication strategies in reconfigurable hardware,” Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, pp. 461–468, 2011. View at Publisher · View at Google Scholar
  • Guillermo Botella, Jose Antonio Martin H, Matilde Santos, and Uwe Meyer-Baese, “FPGA-Based Multimodal Embedded Sensor System Integrating Low- and Mid-Level Vision,” Sensors, vol. 11, no. 8, pp. 8164–8179, 2011. View at Publisher · View at Google Scholar
  • Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, and Toshinori Sueyoshi, “A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core,” Acm Transactions On Reconfigurable Technology And Systems, vol. 4, no. 1, 2010. View at Publisher · View at Google Scholar
  • Zhaoyi Wei, Dah-Jye Lee, Brent E. Nelson, and James K. Archibald, “Hardware-Friendly Vision Algorithms for Embedded Obstacle Detection Applications,” Ieee Transactions On Circuits And Systems For Video Technology, vol. 20, no. 11, pp. 1577–1589, 2010. View at Publisher · View at Google Scholar
  • Guillermo Botella, Antonio Garcia, Manuel Rodriguez-Alvarez, Eduardo Ros, Uwe Meyer-Baese, and María C. Molina, “Robust Bioinspired Architecture for Optical-Flow Computation,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 4, pp. 616–629, 2010. View at Publisher · View at Google Scholar
  • Chun-Lung Hsu, Yu-Sheng Huang, and Fong-Chao Lee, “Interlaced switch boxes placement for three-dimensional FPGA architecture design,” International Journal of Circuit Theory and Applications, vol. 40, no. 5, pp. 489–502, 2010. View at Publisher · View at Google Scholar
  • Daniel Llamocca, Marios Pattichis, and G. Alonzo Vera, “Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic,” International Journal of Reconfigurable Computing, vol. 2010, pp. 1–14, 2010. View at Publisher · View at Google Scholar
  • Taho Dorta, Jaime Jiménez, José Luis Martín, Unai Bidarte, and Armando Astarloa, “Reconfigurable Multiprocessor Systems: A Review,” International Journal of Reconfigurable Computing, vol. 2010, pp. 1–10, 2010. View at Publisher · View at Google Scholar
  • Vitor de Paulo, and Cristinel Ababei, “3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans,” International Journal of Reconfigurable Computing, vol. 2010, pp. 1–12, 2010. View at Publisher · View at Google Scholar
  • Nathalie Bochard, Florent Bernard, Viktor Fischer, and Boyan Valtchanov, “True-Randomness and Pseudo-Randomness in Ring Oscillator-Based True Random Number Generators,” International Journal of Reconfigurable Computing, vol. 2010, pp. 1–13, 2010. View at Publisher · View at Google Scholar
  • Peng Lei, Omkar Dandekar, David Widlus, and Raj Shekhar, “Incorporation of Preprocedural PET into CT-Guided Radiofrequency Ablation of Hepatic Metastases: a Nonrigid Image Registration Validation Study,” Journal Of Digital Imaging, vol. 23, no. 6, pp. 780–792, 2010. View at Publisher · View at Google Scholar
  • M. Tomasi, F. Barranco, M. Vanegas, J. Díaz, and E. Ros, “Fine grain pipeline architecture for high performance phase-based optical flow computation,” Journal of Systems Architecture, vol. 56, no. 11, pp. 577–587, 2010. View at Publisher · View at Google Scholar
  • Xun Zhang, Wassim Jouini, Pierre Leray, and Jacques Palicot, “Temperature-power consumption relationship and hot-spot migration for FPGA-based system,” Proceedings - 2010 IEEE/ACM International Conference on Green Computing and Communications, GreenCom 2010, 2010 IEEE/ACM International Conference on Cyber, Physical and Social Computing, CPSCom 2010, pp. 392–397, 2010. View at Publisher · View at Google Scholar
  • Ludovic Devaux, Sebastien Pillement, Daniel Chillet, and Didier Demigny, “R2NoC: Dynamically reconfigurable routers for flexible Networks on Chip,” Proceedings - 2010 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2010, pp. 376–381, 2010. View at Publisher · View at Google Scholar
  • Luis A. Vera-Salas, Sandra V. Moreno-Tapia, Roque A. Osornio-Rios, and Rene De J. Romero-Troncoso, “Reconfigurable node processing unit for a low-power wireless sensor network,” Proceedings - 2010 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2010, pp. 173–178, 2010. View at Publisher · View at Google Scholar
  • Nazim Fates, “Solving the decentralised gathering problem with a reaction-diffusion-chemotaxis scheme,” Swarm Intelligence, vol. 4, no. 2, pp. 91–115, 2010. View at Publisher · View at Google Scholar
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  • Weisheng Zhao, Jean-Pierre Noziere, Virgile Javerliac, and Claude Chappert, “High Speed, High Stability and Low Power Sensing Amplifier for MTJ/CMOS Hybrid Logic Circuits,” Ieee Transactions On Magnetics, vol. 45, no. 10, pp. 3784–3787, 2009. View at Publisher · View at Google Scholar
  • Kurt Franz Ackermann, Burghard Hoffmann, Leandro Soares Indrusiak, and Manfred Glesner, “Providing Memory Management Abstraction for Self-Reconfigurable Video Processing Platforms,” International Journal of Reconfigurable Computing, vol. 2009, pp. 1–15, 2009. View at Publisher · View at Google Scholar