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Citations to this Journal [225 citations: 101–200 of 204 articles]

Articles published in International Journal of Reconfigurable Computing have been cited 225 times. The following is a list of the 204 articles that have cited the articles published in International Journal of Reconfigurable Computing.

  • Sol Pedre, Tomáš Krajník, Elías Todorovich, and Patricia Borensztejn, “Accelerating embedded image processing for real time: a case study,” Journal of Real-Time Image Processing, 2013. View at Publisher · View at Google Scholar
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  • Sandeep Pande, Fearghal Morgan, Gerard Smit, Tom Bruintjes, Jochem Rutgers, Brian McGinley, Seamus Cawley, Jim Harkin, and Liam McDaid, “Fixed latency on-chip interconnect for hardware spiking neural network architectures,” Parallel Computing, vol. 39, no. 9, pp. 357–371, 2013. View at Publisher · View at Google Scholar
  • David P. Rosin, Damien Rontani, and Daniel J. Gauthier, “Ultrafast physical generation of random numbers using hybrid Boolean networks,” Physical Review E, vol. 87, no. 4, 2013. View at Publisher · View at Google Scholar
  • Ricardo Finger, Patricio Mena, Nicolas Reyes, Rafael Rodriguez, and Leonardo Bronfman, “A Calibrated Digital Sideband Separating Spectrometer for Radio Astronomy Applications,” Publications Of The Astronomical Society Of The Pacific, vol. 125, no. 925, pp. 263–269, 2013. View at Publisher · View at Google Scholar
  • Rong Ren, Jianguo Wei, Eduardo Juarez, Matias Garrido, Cesar Sanz, and Fernando Pescador, “A PMC-driven Methodology for Energy Estimation in RVC-CAL Video Codec Specifications,” Signal Processing: Image Communication, 2013. View at Publisher · View at Google Scholar
  • Kostas Siozios, Vasilis F. Pavlidis, and Dimitrios Soudris, “A Novel Framework for Exploring 3-D FPGAs with Heterogeneous Interconnect Fabric,” Acm Transactions On Reconfigurable Technology And Systems, vol. 5, no. 1, 2012. View at Publisher · View at Google Scholar
  • Gustavo Sanchez, Marcel Corrêa, Diego Noble, Marcelo Porto, Sergio Bampi, and Luciano Agostini, “Hardware design focusing in the tradeoff cost versus quality for the H.264/AVC fractional motion estimation targeting high definition videos,” Analog Integrated Circuits and Signal Processing, vol. 73, no. 3, pp. 931–944, 2012. View at Publisher · View at Google Scholar
  • Teemu Pitkänen, Peter Jamieson, Tobias Becker, Sami Moisio, and Jarmo Takala, “Power consumption benchmarking for reconfigurable platforms,” Analog Integrated Circuits and Signal Processing, vol. 73, no. 2, pp. 649–659, 2012. View at Publisher · View at Google Scholar
  • Martin Gebser, Benjamin Kaufmann, and Torsten Schaub, “Conflict-driven answer set solving: From theory to practice,” Artificial Intelligence, vol. 187-188, pp. 52–89, 2012. View at Publisher · View at Google Scholar
  • Stefan Wildermann, Felix Reimann, Daniel Ziener, and Jürgen Teich, “Symbolic system-level design methodology for multi-mode reconfigurable systems,” Design Automation for Embedded Systems, 2012. View at Publisher · View at Google Scholar
  • Manel Hentati, Samya Elaoud, Yassine Aoudni, Jean-Francois Nezan, and Mohamed Abid, “An efficient Resource Management to optimize the placement of hardware task on FPGA in the RVC framework,” Design Automation for Embedded Systems, vol. 16, no. 4, pp. 363–380, 2012. View at Publisher · View at Google Scholar
  • Vaibhav Garg, Ravi Shekhar, and John G. Harris, “Spiking Neuron Computation With the Time Machine,” Ieee Transactions On Biomedical Circuits And Systems, vol. 6, no. 2, pp. 142–155, 2012. View at Publisher · View at Google Scholar
  • ChiWai Yu, Alastair M. Smith, Wayne Luk, Philip H. W. Leong, and Steven J. E. Wilton, “Optimizing Floating Point Units in Hybrid FPGAs,” Ieee Transactions on Very Large Scale Integration (vlsi) Systems, vol. 20, no. 7, pp. 1295–1303, 2012. View at Publisher · View at Google Scholar
  • Yoshihiro Ichinomiya, Tsuyoshi Kimura, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, and Toshinori Sueyoshi, “Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration,” Ieice Transactions On Fundamentals Of Electronics Communications And Comput, vol. E95A, no. 12, pp. 2347–2356, 2012. View at Publisher · View at Google Scholar
  • Shingo Yoshizawa, and Yoshikazu Miyanaga, “Design of Area- and Power-Efficient Pipeline FFT Processors for 8x8 MIMO-OFDM Systems,” Ieice Transactions On Fundamentals Of Electronics Communications And Comput, vol. E95A, no. 2, pp. 550–558, 2012. View at Publisher · View at Google Scholar
  • Motoki Amagasaki, Yasuhiro Okamoto, Qian Zhao, and Toshinori Sueyoshi, “COGRE: A Novel Compact Logic Cell Architecture for Area Minimization,” Ieice Transactions on Information and Systems, vol. E95D, no. 2, pp. 294–302, 2012. View at Publisher · View at Google Scholar
  • Kazuki Inoue, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, and Toshinori Sueyoshi, “An Easily Testable Routing Architecture and Prototype Chip,” Ieice Transactions On Information And Systems, vol. E95D, no. 2, pp. 303–313, 2012. View at Publisher · View at Google Scholar
  • Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, and Takashi Ishiguro, “A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks,” Ieice Transactions On Information And Systems, vol. E95D, no. 2, pp. 324–334, 2012. View at Publisher · View at Google Scholar
  • Hisashi Hata, and Shuichi Ichiawa, “FPGA Implementation of Metastability-Based True Random Number Generator,” Ieice Transactions On Information And Systems, vol. E95D, no. 2, pp. 426–436, 2012. View at Publisher · View at Google Scholar
  • F. Duhem, F. Muller, and P. Lorenzini, “Reconfiguration time overhead on field programmable gate arrays: reduction and cost model,” Iet Computers And Digital Techniques, vol. 6, no. 2, pp. 105–113, 2012. View at Publisher · View at Google Scholar
  • S. Gao, D. Al-Khalili, N. Chabini, and P. Langlois, “Asymmetric large size multipliers with optimised FPGA resource utilisation,” Iet Computers And Digital Techniques, vol. 6, no. 6, pp. 372–383, 2012. View at Publisher · View at Google Scholar
  • Placido Rogerio Pinheiro, Andre Luis Vasconcelos Coelho, Alexei Barbosa Aguiar, and Alvaro de Menezes Sobreira Neto, “Towards Aid by Generate and Solve Methodology: Application in the Problem of Coverage and Connectivity in Wireless Sensor Networks,” International Journal of Distributed Sensor Networks, vol. 2012, pp. 1–11, 2012. View at Publisher · View at Google Scholar
  • Hanaa M. Hussain, Khaled Benkrid, Ali Ebrahim, Ahmet T. Erdogan, and Huseyin Seker, “Novel dynamic partial reconfiguration implementation of K-means clustering on FPGAs: Comparative results with GPPs and GPUs,” International Journal of Reconfigurable Computing, vol. 2012, 2012. View at Publisher · View at Google Scholar
  • Jones Y. Mori, Janier Arias-Garcia, Camilo Sánchez-Ferreira, Daniel M. Muñoz, Carlos H. Llanos, and J. M. S. T. Motta, “An FPGA-Based Omnidirectional Vision Sensor for Motion Detection on Mobile Robots,” International Journal of Reconfigurable Computing, vol. 2012, pp. 1–16, 2012. View at Publisher · View at Google Scholar
  • Gustavo Sanchez, Felipe Sampaio, Marcelo Porto, Sergio Bampi, and Luciano Agostini, “DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation,” International Journal of Reconfigurable Computing, vol. 2012, pp. 1–12, 2012. View at Publisher · View at Google Scholar
  • Ra Inta, David J. Bowman, and Susan M. Scott, “The “Chimera”: An Off-The-Shelf CPU/GPGPU/FPGA Hybrid Computing Platform,” International Journal of Reconfigurable Computing, vol. 2012, pp. 1–10, 2012. View at Publisher · View at Google Scholar
  • Lukas Meder, Stephan Werner, Oliver Oey, Jürgen Becker, Michael Hübner, and Diana Göhringer, “Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration,” International Journal of Reconfigurable Computing, vol. 2012, pp. 1–14, 2012. View at Publisher · View at Google Scholar
  • Christian de Schryver, Daniel Schmidt, Norbert Wehn, Elke Korn, Henning Marxen, Anton Kostiuk, and Ralf Korn, “A Hardware Efficient Random Number Generator for Nonuniform Distributions with Arbitrary Precision,” International Journal of Reconfigurable Computing, vol. 2012, pp. 1–11, 2012. View at Publisher · View at Google Scholar
  • Kaveh Aasaraai, and Andreas Moshovos, “NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution,” International Journal of Reconfigurable Computing, vol. 2012, pp. 1–12, 2012. View at Publisher · View at Google Scholar
  • Yi Zhan, and Tadahiro Kuroda, “Wearable sensor-based human activity recognition from environmental background sounds,” Journal of Ambient Intelligence and Humanized Computing, 2012. View at Publisher · View at Google Scholar
  • Yousri Ouerhani, Maher Jridi, and Ayman Alfalou, “Area-Delay Efficient Fft Architecture Using Parallel Processing And New Memory Sharing Technique,” Journal Of Circuits Systems And Computers, vol. 21, no. 6, 2012. View at Publisher · View at Google Scholar
  • Jintao Yu, Jianmin Pang, Zheng Shan, and Haoran Guo, “On-the-fly data transmission for FPGA acceleration: A case study,” Journal of Convergence Information Technology, vol. 7, no. 19, pp. 418–425, 2012. View at Publisher · View at Google Scholar
  • John A. Kalomiros, “Dense disparity features for fast stereo vision,” Journal of Electronic Imaging, vol. 21, no. 4, 2012. View at Publisher · View at Google Scholar
  • Sardar Anisul Haque, and Marc Moreno Maza, “Plain polynomial arithmetic on GPU,” Journal of Physics: Conference Series, vol. 385, no. 1, 2012. View at Publisher · View at Google Scholar
  • Matthias Birk, Michael Zapf, Matthias Balzer, Nicole Ruiter, and Jürgen Becker, “A comprehensive comparison of GPU- and FPGA-based acceleration of reflection image reconstruction for 3D ultrasound computer tomography,” Journal of Real-Time Image Processing, vol. 9, no. 1, pp. 159–170, 2012. View at Publisher · View at Google Scholar
  • Pierre-Henri Horrein, Christine Hennebert, and Frédéric Pétrot, “An environment for (re)configuration and execution management of heterogeneous flexible radio platforms,” Microprocessors and Microsystems, 2012. View at Publisher · View at Google Scholar
  • Snaider Carrillo, Jim Harkin, Liam McDaid, Sandeep Pande, Seamus Cawley, Brian McGinley, and Fearghal Morgan, “Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers,” Neural Networks, vol. 33, pp. 42–57, 2012. View at Publisher · View at Google Scholar
  • Andrew G. Schmidt, Siddhartha Datta, Ashwin A. Mendon, and Ron Sass, “Investigation into scaling I/O bound streaming applications productively with an all-FPGA cluster,” Parallel Computing, vol. 38, no. 8, pp. 344–364, 2012. View at Publisher · View at Google Scholar
  • Emanuele Cannella, Onur Derin, Paolo Meloni, Giuseppe Tuveri, and Todor Stefanov, “Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks,” VLSI Design, vol. 2012, pp. 1–17, 2012. View at Publisher · View at Google Scholar
  • Emanuele Cannella, Lorenzo Di Gregorio, Leandro Fiorin, Menno Lindwer, Paolo Melonr, Olaf Neugebauer, and Andy Pimentel, “Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?,” 2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2011, pp. 120–129, 2011. View at Publisher · View at Google Scholar
  • Ekaterina Gonina, Gerald Friedland, Henry Cook, and Kurt Keutzer, “Fast speaker diarization using a high-level scripting language,” 2011 IEEE Workshop on Automatic Speech Recognition and Understanding, ASRU 2011, Proceedings, pp. 553–558, 2011. View at Publisher · View at Google Scholar
  • Ikbel Belaid, Fabrice Muller, and Maher Benjemaa, “Optimal static scheduling of real-time dependent tasks on reconfigurable hardware devices,” 2011 International Conference on Communications, Computing and Control Applications, CCCA 2011, 2011. View at Publisher · View at Google Scholar
  • Martin Kumm, and Peter Zipf, “High speed low complexity FPGA-based FIR filters using pipelined adder graphs,” 2011 International Conference on Field-Programmable Technology, FPT 2011, 2011. View at Publisher · View at Google Scholar
  • Gian Carlo Cardarilli, Marco Re, Ilir Shuli, and Lorenzo Simone, “Partial reconfiguration in the implementation of autonomous radio receivers for space,” 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2011 - Proceedings, 2011. View at Publisher · View at Google Scholar
  • Hung-Manh Pham, Ludovic Devaux, and Sébastien Pillement, “Re2DA: Reliable and reconfigurable dynamic architecture,” 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2011 - Proceedings, 2011. View at Publisher · View at Google Scholar
  • Scott Lloyd, and Quinn O. Snell, “Accelerated large-scale multiple sequence alignment,” Bmc Bioinformatics, vol. 12, 2011. View at Publisher · View at Google Scholar
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  • Matthias Birk, Alexander Guth, Michael Zapf, Matthias Balzer, Nicole Ruiter, Michael Hübner, and Jürgen Becker, “Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing,” Conference on Design and Architectures for Signal and Image Processing, DASIP, pp. 67–74, 2011. View at Publisher · View at Google Scholar
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