Jürgen Becker

Michael Hübner

Roger Woods

Philip Leong

Robert Esser

Lionel Torres

Current Trends on Reconfigurable Computing

In real-time signal processing, a single application often has multiple computationally intensive kernels that can benefit from acceleration using custom or reconfigurable hardware platforms, such as field-programmable gate arrays (FPGAs). For adaptive utilization of resources at run time, FPGAs with capabilities for dynamic reconfiguration are emerging. In this context, it is useful for designers to derive sets of efficient configurations that trade off application performance with fabric resources. Such sets can be maintained at run time so that the best available design tradeoff is used. Finding a single, optimized configuration is difficult, and generating a family of optimized configurations suitable for different run-time scenarios is even more challenging. We present a novel multiobjective wordlength optimization strategy developed through FPGA-based implementation of a representative computationally intensive image processing application: medical image registration. Tradeoffs between FPGA resources and implementation accuracy are explored, and Pareto-optimized wordlength configurations are systematically identified. We also compare search methods for finding Pareto-optimized design configurations and demonstrate the applicability of search based on evolutionary techniques for identifying superior multiobjective tradeoff curves. We demonstrate feasibility of this approach in the context of FPGA-based medical image registration; however, it may be adapted to a wide range of signal processing applications.

Omkar Dandekar

William Plishker

Shuvra S. Bhattacharyya

Raj Shekhar

Multiobjective Optimization for Reconfigurable Implementation of Medical Image Registration

In current reconfigurable architectures, the interconnection structures increasingly contribute more to the delay and power consumption. The demand for increased clock frequencies and logic density (smaller area footprint) makes the problem even more important. Three-dimensional (3D) architectures are able to alleviate this problem by accommodating a number of functional layers, each of which might be fabricated in different technology. However, the benefits of such integration technology have not been sufficiently explored yet. In this paper, we propose a software-supported methodology for exploring and evaluating alternative interconnection schemes for 3D FPGAs. In order to support the proposed methodology, three new CAD tools were developed (part of the 3D MEANDER Design Framework). During our exploration, we study the impact of vertical interconnection between functional layers in a number of design parameters. More specifically, the average gains in operation frequency, power consumption, and wirelength are 35%, 32%, and 13%, respectively, compared to existing 2D FPGAs with identical logic resources. Also, we achieve higher utilization ratio for the vertical interconnections compared to existing approaches by 8% for designing 3D FPGAs, leading to cheaper and more reliable devices.

Kostas Siozios

Alexandros Bartzas

Dimitrios Soudris

Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology

This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design. The nonvolatility of the latter is achieved through the use of magnetic tunneling junctions (MTJs) in the MRAM cell. A thermally assisted switching scheme helps to reduce power consumption during write operation in comparison to the writing scheme in the FIMS-MTJ device. Moreover, the nonvolatility of such a design based on either an FIMS or a TAS writing scheme should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM-based FPGAs. A real-time reconfigurable (RTR) micro-FPGA using FIMS-MRAM or TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.

Y. Guillemenet

L. Torres

G. Sassatelli

N. Bruchon

On the Use of Magnetic RAMs in Field-Programmable Gate Arrays

Reconfigurable logic devices (RLDs) are classified as the fine-grained or coarse-grained type based on their basic logic cell architecture. In general, each architecture has its own advantage. Therefore, it is difficult to achieve a balance between the operation speed and implementation area in various applications. In the present paper, we propose a variable grain logic cell (VGLC) architecture, which consists of a 4-bit ripple carry adder with configuration  memory bits and develop a technology mapping tool. The key feature of the VGLC architecture is that the variable granularity is a tradeoff between coarse-grained and fine-grained types required for the implementation arithmetic and random logic, respectively. Finally, we evaluate the proposed logic cell using the newly developed technology mapping tool, which improves
logic depth by 31% and reduces the number of configuration data by 55% on average, as compared to the Virtex-4 logic cell architecture.

Motoki Amagasaki

Ryoichi Yamaguchi

Masahiro Koga

Masahiro Iida

Toshinori Sueyoshi

An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture

Applications that leverage the dynamic partial reconfigurability of modern FPGAs are
few, owing in large part to the lack of suitable tools and techniques to create them. While
the trend in digital design is towards higher levels of design abstractions, forgoing hardware
description languages in some cases for high-level languages, the development of a reconfigurable
design requires developers to work at a low level and contend with many poorly
documented architecture-specific aspects. This paper discusses the creation of a high-level
development environment for reconfigurable designs that leverage an existing high-level synthesis
tool to enable the design, simulation, and implementation of dynamically reconfigurable
hardware solely from a specification written in C. Unlike previous attempts, this approach
encompasses the entirety of design and implementation, enables self-re-configuration
through an embedded controller, and inherently handles partial reconfiguration. Benchmarking
numbers are provided, which validate the productivity enhancements this approach
provides.

Stephen Craven

Peter Athanas

Dynamic Hardware Development

Transaction-level modeling (TLM) is a promising technique to deal with the increasing complexity of modern embedded systems. This model allows a system designer to model a complete application, composed of hardware and software parts, at several levels of abstraction. For this purpose, we use systemC, which is proposed as a standardized modeling language. This paper presents a transaction-level modeling cosimulation methodology for modeling, validating, and verifying our embedded open architecture platform. The proposed platform is an open source multiprocessor system-on-chip (MPSoC) platform, integrated under the synthesis tool for adaptive and reconfigurable system-on-chip (STARSoC) environment. It relies on the integration between an open source instruction set simulators (ISSs), OR1Ksim platform, and the systemC simulation environment which contains other components (wishbone bus, memories, <svg style="vertical-align:-0.13794pt;width:18.362499px;" id="M1" height="1.8625" version="1.1" viewBox="0 0 18.362499 1.8625" width="18.362499" xmlns="http://www.w3.org/2000/svg">
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</svg>, etc.). The aim of this work is to provide designers with the possibility of faster and efficient architecture exploration at a higher level of abstractions, starting from an algorithmic description to implementation details.

Sami Boukhechem

El-Bay Bourennane

SystemC Transaction-Level Modeling of an MPSoC Platform Based on an Open Source ISS by Using Interprocess Communication

With forecasted hundreds of processing elements
(PEs), future embedded systems will be able
to handle multiple applications with very diverse
running constraints. Systems will integrate distributed
decision capabilities. In order to control
the power and temperature, dynamic voltage
frequency scalings (DVFSs) are applied at PE
level. At system level, it implies to dynamically
manage the different voltage/frequency couples of
each tile to obtain a global optimization. This paper
introduces a scalable multiobjective approach
based on game theory, which adjusts at run-time
the frequency of each PE. It aims at reducing the
tile temperature while maintaining the synchronization
between application tasks. Results show that
the proposed run-time algorithm requires an average
of 20 calculation cycles to find the solution
for a 100-processor platform and reaches equivalent
performances when comparing with an offline
method. Temperature reductions of about 23%
were achieved on a demonstrative test-case.

Diego Puschini

Fabien Clermidy

Pascal Benoit

Gilles Sassatelli

A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC

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International Journal of Reconfigurable Computing aims to serve the large community of researchers and professional engineers working on the theoretical and practical aspects of reconfigurable computing.

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International Journal of Reconfigurable Computing

Current Trends on Reconfigurable Computing

Current Trends on Reconfigurable Computing

Articles

Current Trends on Reconfigurable Computing

Multiobjective Optimization for Reconfigurable Implementation of Medical Image Registration

Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology

On the Use of Magnetic RAMs in Field-Programmable Gate Arrays

An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture

Dynamic Hardware Development

SystemC Transaction-Level Modeling of an MPSoC Platform Based on an Open Source ISS by Using Interprocess Communication

A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC