Since it was first announced in 1965, Moore's law has stood up the test of time, providing exponential increases in computing power for science and engineering problems over time. However, while this law was largely followed through increases in transistor integration levels and clock frequencies, this is no longer possible as power consumption and heat dissipation are becoming major hurdles in the face of further clock frequency increases, the so-called frequency or power wall problem.

In order to keep Moore's law going general-purpose processor manufacturers are now relying on multicore chip technology in which multiple cores run simultaneously on the same chip. While this has the potential to provide considerable speed-up for science and engineering applications, it is also creating a semantic gap between applications, traditionally written in sequential code, and hardware, as multicore technologies need to be programmed in parallel to take advantage of their performance potential.

This semantic gap is also opening a window of opportunity for niche parallel computer technologies such as Field Programmable Gate Arrays (FPGAs) and Graphics Processor units (GPUs) since the problem of parallel programming has to be tackled for general-purpose processors anyway.

The aim of this special issue is to present the latest developments in the area of high-performance computing using reconfigurable hardware, also known as High-Performance Reconfigurable Computing (HPRC). A special emphasis will be put on the opportunities, challenges, and future developments in HPRC, especially in relation to other technologies such as general-purpose multicore processors and GPUs. Potential topics include, but are not limited to:

• Novel high performance and scalable reconfigurable architectures. Submissions on novel heterogeneous computer architectures as well as comparative studies between alternative accelerator technologies, for example, FPGAs versus GPUs, are particularly welcome. Quantitative criteria, for example, speed, energy consumption, and cost of purchase and development, as well as qualitative criteria, for example, ease of maintenance, standardisation, and backward/forward compatibility, should be used in such comparisons
• Novel high performance computing applications and implementations on reconfigurable hardware systems
• Novel software tools for the design, programming, and debugging of high-performance reconfigurable systems. This includes contributions on portable tools and libraries across vendors and technologies, as well as modelling tools for HPRC system design and development

Before submission authors should carefully read over the journal's Author Guidelines, which are located at http://www.hindawi.com/journals/ijrc/guidelines/. Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at http://mts.hindawi.com/ according to the following timetable: