Hardware Configuration to the Aid of Parallel Computation

Call for Papers

FPGAs are on the rise in high-performance computing. In recent years, the configurability, flexibility, and compute capability have thoroughly increased, while these devices maintain a low-power profile. This makes multi-FPGA systems quite attractive for high-performance and highly parallel computing. Field programmable gate arrays are emerging in many areas of high-performance computing, either as tailor-made signal processor, embedded algorithm implementation, systolic array, software accelerator, or application-specific architecture. The programming of FPGAs continues to improve with high-level C-like development environments and low-level development kits for performance tuning. However, the design complexity of FPGAs and their role as building block in a high-performance computing system is subjected to innovative research. Many diverse approaches exist, ranging from novel architectures, hardware-software codesign, evolvable hardware, evolutionary algorithms, reconfigurable computing, to the development of whole compiler, simulation and synthesis frameworks. In this special issue, new and original contributions are invited on parallel computing with FPGAs and the use of reconfiguration to improve parallel computing implementations.

Because of their versatility as an enabling component in parallel architectures, this special issue addresses all areas of FPGAs in parallel computing, in particular methodology, performance analysis, architectures, algorithms, and applications. These aspects are addressed in the ParaFPGA Workshop at the Parco Conference. Authors that presented a paper at this workshop are especially invited to submit an extended version to the journal. Other papers are very welcome as well.

Prospective authors are cordially invited to participate or submit their contribution to the IJRC special issue. Potential topics include, but are not limited to:

• Parallel computing techniques with FPGAs
• Programming environments for FPGAs
• Parallel languages and design tools for very complex FPGA-based designs
• Graphical FPGA development environments
• Speedups and power savings obtained by software to FPGA migration
• FPGA-based acceleration
• Comparison of FPGA performance/power against other forms of parallel computing such as GPUs
• Interconnection networks on FPGAs
• Multi-FPGA cores
• FPGA-based parallel applications

Both research and review papers are welcome.

Before submission authors should carefully read over the journal's Author Guidelines, which are located at http://www.hindawi.com/journals/ijrc/guidelines/. Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at http://mts.hindawi.com/ according to the following timetable:

Lead Guest Editor

• Dirk Stroobandt, Ghent University, Ghent, Belgium

Guest Editors

• Ryan Kastner, University of California, San Diego, CA, USA
• Dionisis Pnevmatikatos, FORTH-ICS, Crete, Greece
• Michael Hübner, Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany