About this Journal Submit a Manuscript Table of Contents
ISRN Electronics
Volume 2013 (2013), Article ID 271316, 7 pages
http://dx.doi.org/10.1155/2013/271316
Research Article

Leakage Power Analysis of Domino XOR Gate

Department of Electronics and Communication, M.N.N.I.T, Allahabad 211004, India

Received 23 November 2012; Accepted 13 December 2012

Academic Editors: M. Hopkinson and V. McGahay

Copyright © 2013 A. K. Pandey et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Two new XOR gates are proposed. First proposed circuits adopt hybrid transistor topology in the pull-down network with all transistors being low threshold voltages. A second proposed circuit adopts hybrid topology with dual threshold voltage transistors. Simulation parameters are measured at 25°C and 110°C. First proposed circuit reduces leakage power consumption up to 50% at 25°C and 58% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 14% as compared to standard N-type domino XOR gate. Similarly, second proposed circuit reduces leakage power consumption up to 73% at 25°C and 90% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 39% as compared to standard N-type domino XOR gate.

1. Introduction

CMOS XOR gates are the fundamental units, it is used in many VLSI applications such as adders and microprocessors. CMOS XOR has complex pull up and pull down network, it is being characterized as high power consumption, large layout area, and low speed [14]. Domino XOR has small layout area, low power consumption, and improved speed as compared to CMOS XOR [57]. Due to its superior performance and low power consumption, domino XOR is being used in many VLSI applications. Standard domino XOR gate requires two phase input signals, one is original and the other is inverted signal. It needs additional inverters to meet the design requirements. The additional inverters not only increase the power consumption but also affect the performance of the circuit.

As technology is scaled down, supply voltages are also scaled down to keep the dynamic power at acceptable levels, and at the same time threshold voltage is also scaled down to meet the performance requirements. However, subthreshold leakage and gate oxide leakage currents are increased exponentially with the scaling of threshold voltage and gate oxide thickness , hence power consumption increases and noise immunity decreases. To solve the problem of high subthreshold leakage current, many circuit level techniques have been implemented including body bias control [8], input vector control [9], transistor stack effect [10], dual CMOS [11], and sleep switch [1214]. Dual domino technique [11] is realized by using low transistor in the evaluation path and high transistor in the precharge path of the circuits. According to Kao, high clock and high inputs (CHIH) are preferable to reduce subthreshold leakage current in dual footless domino gate.

Combination of subthreshold and gate oxide leakage current in footless domino circuit was carried out by Liu and Kursun [1517]. Considering the major effects of gate oxide leakage current on the total leakage current, it shows that at low temperature, clock high and inputs low (CHIL) state is preferable. At high temperature CHIH state is preferable in domino footless circuit. Sleep switch methods are efficient for reducing both subthreshold and gate oxide leakage current. High nMOS switch is added to the dynamic node in domino footless circuit. High clock and active sleep switch suppresses subthreshold leakage current but produces high output of domino gate that places highest gate oxide leakage current to the fan out domino gate [12]. By adding two sleep switches, one at dynamic node and other at output node, both subthtreshold and gate oxide leakage current are reduced [13, 14].

Combination of clock and inputs signal states is provided for footed domino circuits to optimize the total leakage current [18]. According to [18], subthreshold and gate oxide leakage currents are not only function of input states but also clock signal states. If subthreshold is the dominant source, then CHIH state is the best choice. Similarly, if gate oxide leakage current is the dominant source, then clock low and input low (CLIL) state is preferable. Leakage power consumption of the domino circuit is characterized as where is the combination of subthreshold and gate oxide leakage current.

In this paper, two new domino XOR circuits are proposed. First proposed circuit has N and P type mixed transistors in the pull down network and all transistors are low threshold voltage. Second proposed circuit utilizes dual threshold voltage. Rest of the paper is organized as follows. Section 2 discusses the leakage current characteristic of single transistor. Section 3 describes the operation of the standard domino XOR circuits. In Section 4, proposed circuits are discussed in details. In Section 5, simulation results are analyzed and the conclusion is presented in Section 6.

2. Leakage Current Analysis of Single Transistor

The subthreshold and gate oxide leakage currents are shown in Figure 1. Subthreshold leakage current is maximum when transistor is in cut off mode and voltage difference between drain-to-source is maximum and it has reverse edge gate oxide leakage current as shown in Figure 1(a). Gate oxide leakage current has four components: gate-to-channel (), gate-to-drain (), gate-to-source (), and gate-to-body (). Igb is several orders smaller as compared to all three components and it is neglected, Igc is shared between drain and source as shown in Figure 1(b). Gate oxide leakage current is maximum, when transistor is in active mode and the voltage difference between the gate-to-source and gate-to-drain are maximum. To avoid both subthreshold and gate oxide leakage currents, all terminals of a transistor must have same potential as shown in Figure 1(c).

fig1
Figure 1: (a) Maximum subthreshold leakage current state. (b) Maximum gate oxide leakage current state. (c) Condition to avoid both subthreshold and gate oxide leakage current.

The width and length of both an nMOS and a pMOS transistors are set to be 1 μm and .045 um, respectively. Gate oxide leakage of an nMOS transistor is dominant over pMOS transistor because tunneling probability of electron is greater than tunneling probability of hole as shown in Figure 2. The gate oxide leakage current produced by an nMOS transistor is 9.9x to 40.1x times higher than the gate oxide leakage current of a pMOS transistor depending on the voltage difference across the gate oxide [13, 14].

271316.fig.002
Figure 2: Comparison of gate oxide leakage current for an nMOS and pMOS [14].

Variations of subthreshold and gate oxide leakage current of an nMOS with supply voltage at two different temperatures as shown in Figure 3. At 110°C, the subthreshold leakage current is 6.7 times higher than the gate oxide leakage current at 0.8 V supply voltage [13]. Similarly, at the room temperature, the gate oxide leakage current is 2.5 times higher than subthreshold leakage current at 0.8 V.

271316.fig.003
Figure 3: Comparison of subthreshold and gate oxide leakage current of an nMOS at two different temperatures [14].

Comparison of normalized subthreshold leakage current and gate oxide leakage current produced by low- transistor and high- transistor in dual CMOS technology as shown in Table 1 [14]. Here we have taken transistor width as 1 μm, transistor length as 45 nm, low- for nMOS and pMOS are set at 0.22 V and −0.22 V, high- for a nMOS and pMOS are set 0.466 V and −0.4118 V, and power supply is 0.8 V, respectively. For each temperature, the currents are normalized to the subthreshold leakage current produced by the high- pMOS transistor. The gate oxide leakage current of a low- nMOS transistor is 3.30 times and 9.4 times higher than the subthreshold leakage current of a high- pMOS transistor at the high and low temperatures, respectively. The gate oxide leakage current produced by a low- nMOS transistor is 34 times and 30 times higher than the gate oxide leakage current produced by a low- pMOS transistor at 110°C and 25°C. The gate oxide leakage current for pMOS device is lower as compared to an nMOS device with the same width and length with different and the same voltage difference across the gate insulator.

tab1
Table 1: Normalized subthreshold and gate oxide leakage currents of the low- and high- transistors at two different temperatures [14].

Figure 4 shows that subthreshold leakage current produced by the low- transistors is the highest source of leakage current in sub-45 nm technologies at high temperature (110°C). At room temperature (25°C), gate oxide leakage current produced by the low- nMOS is the dominant source of the leakage current. At room temperature, gate oxide leakage current is the dominant contributor and has little dependence on temperature. Subthreshold leakage current increases exponentially with temperature and it is dominant for high temperature. Relative contribution of gate oxide and subthreshold leakage currents is also dependent on fan-in, structure of the PDN, and inputs of the fan-in of domino circuits.

271316.fig.004
Figure 4: Comparison of subthreshold and gate oxide leakage current of low- and high- transistors at two different temperatures.

3. Standard XOR Gate

The standard N-type domino XOR gate (DXN) as shown in Figure 5. Transistor M2 works as keeper. Here pull down network consists of all N-type transistors [5]. The dynamic node gives XNOR gate logic and output node gives XOR gate logic . The clock signal divides the circuit operation into two operating phases, precharge and evaluation phase. In precharge phase, clock is low, dynamic node is charged to by pull-up transistor M1, M5 turned OFF so no direct DC current flows from power supply to ground. M5 avoids short circuit current in the circuit. During evaluation phase, clock is high, the pull-up transistor is cut off and footer transistor M5 is ON. Depending upon the inputs in the pull-down network, a conditional path is established between the dynamic node and ground. If , or , , dynamic node is discharged to low voltage and output node is charged to high voltage. Output remains low for the rest of the input states.

271316.fig.005
Figure 5: Standard N-type domino XOR gate (DXN) [5].

The standard P-type domino XOR gate as shown in Figure 6. Here pull-up network consists of all P-type transistors [5]. Transistor M2 works as keeper. In precharge phase, clock is low, depending upon on the inputs of the pull-up network, a conditional path is established between the power supply and the dynamic node. If , or , , dynamic node is charged to high voltage and output node is discharged to low voltage. During evaluation phase, dynamic node is discharged to low voltage.

271316.fig.006
Figure 6: Standard P-type domino XOR gate (DXP) [5].

P-type domino XOR gate has a great advantage as compared to N-type domino XOR. It effectively suppresses both subthreshold and gate oxide leakage current at the expense of speed. N-type domino circuit has higher speed and higher power consumption, and P-type domino circuit has lower speed and lower power consumption. Drawbacks of standard N-type or P-type is that the input signals must be two phases, original and its inverted signals. Extra inverters must be added in the circuit to get inverted signal of original signal. Adding inverter increases the extra power consumption and propagation delay which extremely affects the performance of the domino XOR gate.

4. Proposed XOR Structures

Focusing on the advantage of an N-type transistor having high speed and a P-type transistor having low power consumption. The proposed circuits utilized the advantage of both N-type and P-type transistors.

4.1. Proposed Circuit 1 (DXHL)

This technique adopts N and P type hybrid transistors in the pull-down network and all the transistors are low threshold voltage (DXHL) as shown in Figure 7. In this circuit, parallel combination of P-type M6, M7 and N-type M8, M9 transistors are connected in series. Here additional inverters are not required to provide inverted input signals. During precharge phase, dynamic node is charged to and output is discharged to low voltage. During evaluation phase, if inputs , or , , dynamic node is discharged to low voltage and output node is charged to high voltage. For other combination of inputs, dynamic node is high and output node is low. Here DXHL requires single phase input signal and has small circuit area as compared to standard N-type and P-type domino XOR gate. From the circuit, it is clear that removing extra inverter reduces the power consumption. Drawback of this technique is that it has lower speed as compared to standard N-type or P-type domino XOR gate. Dynamic node gives XNOR logic

271316.fig.007
Figure 7: Hybrid domino XOR gate with low threshold voltage transistors (DXHL).

Output node gives XOR logic

4.2. Proposed Circuit 2 (DXHD)

Hybrid XOR gate with dual threshold voltage domino gate (DXHD) as shown in Figure 8. Here all transistors that can be activated during precharge phase have high threshold voltage transistors and others have low threshold voltage transistors that determine the speed of this circuit. Subthreshold and gate oxide leakage current of all the high transistors are lesser than low transistor. In precharge mode, turning ON the high- pull-up transistor. When clock is high, operation of this circuit is similar to previous technique.

271316.fig.008
Figure 8: Hybrid domino XOR gate with dual threshold voltage transistors (DXHD).

5. Simulation Results

In this section, proposed circuits (DXHL and DXHD) and existing circuits (DXN and DXP) are simulated, respectively, based on 45 nm models [19] using HSPICE tool. 1 GHz clock frequency is applied to all the circuits with load capacitance 1 fF. Low threshold voltage for an nMOS and a pMOS transistor are set as 0.22 V and −0.22 V, respectively. High threshold voltage for an nMOS and a pMOS transistor and supply voltage are set as 0.466 V, −0.4118 V, and 0.8 V, respectively. To have reasonable comparison, all the circuits have similar size. Leakage power consumption is measured at 25°C and at 110°C, respectively. Active mode power consumption and A.C noise margin are measured at 110°C.

At room temperature, gate oxide leakage current is dominant over subthreshold leakage current. The leakage power consumption of proposed circuits and existing circuits in four clock input vectors with clock states at 25°C are listed in Table 2. It is shown that proposed circuits have lesser leakage power consumption as compared to the existing circuits. The reason is that DXHL adopts hybrid P and N transistors in the pull-down network, and DXHD adopts hybrid P and N transistors with dual threshold voltage. These techniques do not use extra inverters, as a result leakage power consumption is reduced. The optimal leakage power consumption states of DXN, DXP, DXHL, and DXHD are , , and , respectively. It is clear from the Table, DXHL reduces leakage power consumption by 49.7% and 45.1% as compared to DXN and DXP, respectively. Similarly, DXHD reduces leakage power consumption by 73.6%, 71.2%, and 47.5% as compared to DXN, DXP, and DXHL, respectively. Therefore, at low temperature, DXHD has minimum leakage power consumption compared to other techniques.

tab2
Table 2: Leakage power consumption (μW) of four XOR circuits in different Input States and Clock States at 25°C.

At high temperature, subthreshold leakage current is dominant over gate oxide leakage current. The leakage power consumption of proposed circuits and existing circuits in four clock input vectors with clock states at 110°C are listed in Table 3. It is shown that DXHL and DXHD have lesser leakage power consumption as compared to the existing circuits. The optimal leakage current states of DXN,DXP, DXHL, and DXHD are , , , and , respectively. DXHL reduces leakage power consumption by 58.4% and 53.7% as compared to DXN and DXP, respectively. Similarly, DXHD reduces leakage power consumption by 90.7%, 89.7%, and 77.8% as compared to DXN, DXP, and DXHL, respectively. Therefore, at high temperature, DXHD has minimum leakage power consumption compared to other techniques.

tab3
Table 3: Leakage power consumption (μW) of four XOR circuits in different Input States and Clock States at 110°C.

A.C noise margin is defined as the level of noise signal for which output is reduced by 10% of its maximum value. Noise signal is applied to all inputs of the circuits and to be set as 1 GHz square wave with 60% duty cycle at 110°C. A.C noise margin is calculated for the proposed circuits and existing circuits are listed in Table 4. DXHD increased A.C noise margin by 18.18%, 12.72%, and 5.45% as compared to DXN, DXP, and DXHL circuits.

tab4
Table 4: A.C noise margin of four XOR circuits at 110°C.

Active mode power consumption is measured when a conditional path is established between the dynamic node and ground. Figure 9 shows comparison of normalized active mode power consumption and normalized leakage power consumption of optimal state of four XOR circuits at 110°C. It is seen from the figure that DXHD reduces active mode power consumption by 39.12%, 35.38%, and 29.04% as compared to DXN, DXP, and DXHL circuits. DXHD technique has lowest active power as compared to other techniques. DXHD technique better performance as compared to other techniques at the expense of the speed.

271316.fig.009
Figure 9: Comparision of normalized active mode power consumption and optimal leakage power consumption at 110°C.

6. Conclusion

At room temperature, gate oxide leakage current is dominant over subthreshold leakage current. Similarly, at high temperature, subthreshold leakage current is dominant over gate oxide leakage current. In a 45 nm CMOS technology, both subthreshold and gate oxide leakage current are needed to be suppressed. In this paper, two new XOR circuits are proposed to reduce leakage power consumption and active mode power consumption as compared to standard XOR circuits. First proposed circuit utilizes hybrid N- and P-type transistors in the pull-down network with all transistors are low threshold voltage. Second proposed circuit utilizes hybrid N and P type transistors in the pull-down network with dual threshold voltage transistors. Circuits are simulated in HSPICE tool based on 45 nm technology.

At room temperature, first proposed circuit reduces leakage power consumption by 49.7% and 45.1% as compared to N-type domino XOR and P-type domino XOR respectively. Second proposed circuit reduces leakage power consumption by 73.6%, 71.2%, and 47.5% as compared to standard N-type domino XOR, P-type XOR, and proposed circuit1, respectively. At high temperature, first proposed circuit reduces leakage power consumption by 58.4% and 53.7% as compared to N-type domino XOR and P-type domino XOR respectively. Second proposed circuit reduces leakage power consumption by 90.7%, 89.7%, and 77.8% as compared to standard N-type domino XOR, P-type XOR, and proposed circuit1, respectively. Proposed circuit 2 reduces active mode power consumption by 39.12%, 35.38%, and 29.04% as compared to standard N-type domino XOR, P-type domino XOR, and proposed circuit 1. Proposed circuit 2 increases A.C noise margin by 18.18%, 12.72% and 5.45% as compared to standard N-type domino XOR, P-type domino XOR, and proposed circuit 1.

References

  1. S. S. Mishra, S. Wairya, R. K. Nagaria, and S. Tiwari, “New deisgn methodologies for high speed low power XOR-XNOR circuits,” Journal of World Academy of Science, Engineering and Technology, vol. 55, no. 35, pp. 200–206, 2009.
  2. S. R. Chowdhary, A. Banerjee, A. Roy, and H. Saha, “A high speed 8 transistor full adder design using novel 3 transistor XOR gates,” International Journal of Electrical and Computer Engineering, vol. 3, no. 12, pp. 784–790, 2008.
  3. S. Wairya, R. K. Nagaria, and S. Tiwari, “Comparative performance analysis of XOR-XNOR function based high speed CMOS full adder circuits for low voltage VLSI design,” International Journal of VLSI Design and Communication Systems, vol. 3, no. 2, pp. 221–242, 2012. View at Publisher · View at Google Scholar
  4. S. Wairya, G. Singh, Vishant, R. K. Nagaria, and S. Tiwari, “Design Analysis of XOR, (4T) based voltage CMOS full adder cell,” in Proceedings of IEEE International Conference on Current Trends in Technology (NUiCONE '11), pp. 1–7, Institute of Technology, Nirma University, Ahmedabad, India, December 2011.
  5. J. Wang, N. Gong, L. Hou, X. Peng, S. Geng, and W. Wu, “Low power and high performance dynamic CMOS XOR/XNOR gate design,” Microelectronic Engineering, vol. 88, no. 8, pp. 2781–2784, 2011. View at Publisher · View at Google Scholar · View at Scopus
  6. B. Guo, T. Ma, and Y. Zhang, “Design of a novel domino XNOR gate for 32 nm-node CMOS technology,” IEEE Proceedings, pp. 1–4, 2011.
  7. S. Wairya, R. K. Nagaria, and S. Tiwari, “Performance analysis of high speed hybrid CMOS full adder circuits for low voltage VLSI design,” VLSI Design, vol. 2012, Article ID 173079, 18 pages, 2012. View at Publisher · View at Google Scholar
  8. A. Keshavarzi, S. Narendra, S. Borkar, C. Hawkins, K. Roy, and V. De, “Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's,” in Proceedings of the International Conference on Low Power Electronics and Design (ISLPED '99), pp. 252–254, August 1999. View at Scopus
  9. A. Abdollahi, F. Fallah, and M. Pedram, “Leakage current reduction in CMOS VLSI circuits by input vector control,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 2, pp. 140–154, 2004. View at Publisher · View at Google Scholar · View at Scopus
  10. S. Heo and K. Asanović, “Leakage-biased domino circuits for dynamic fine-grain leakage reduction,” in Proceedings of Symposium on VLSI Circuits Digest of Technical Papers, pp. 316–319, Honolulu, Hawaii, USA, June 2002. View at Scopus
  11. J. T. Kao and A. P. Chandrakasan, “Dual-threshold voltage techniques for low-power digital circuits,” IEEE Journal of Solid-State Circuits, vol. 35, no. 7, pp. 1009–1018, 2000. View at Publisher · View at Google Scholar · View at Scopus
  12. V. Kursun and E. G. Friedman, “Sleep switch dual threshold voltage domino logic with reduced standby leakage current,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 5, pp. 485–496, 2004. View at Publisher · View at Google Scholar · View at Scopus
  13. Z. Liu and V. Kursun, “Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current,” Microelectronics Journal, vol. 37, no. 8, pp. 812–820, 2006. View at Publisher · View at Google Scholar · View at Scopus
  14. Z. Liu and V. Kursun, “PMOS-only sleep switch dual-threshold voltage domino logic in sub-65-nm CMOS technologies,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 12, pp. 1311–1319, 2007. View at Publisher · View at Google Scholar · View at Scopus
  15. Z. Liu and V. Kursun, “Leakage power characteristics of dynamic circuits in nanometer CMOS technologies,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 8, pp. 692–696, 2006. View at Publisher · View at Google Scholar · View at Scopus
  16. Z. Liu and V. Kursun, “Shifted leakage power characteristics of dynamic circuits due to gate oxide tunneling,” in Proceedings of IEEE International SOC Conference, pp. 151–154, Herndon, Va, USA, September 2005. View at Scopus
  17. J. Wang, N. Gong, L. Hou, X. Peng, R. Sridhar, and W. Wu, “Leakage current, active power, and delay analysis of dynamic dual VtCMOS circuits under P-V-T fluctuations,” Microelectronics Reliability, vol. 51, pp. 1498–1502, 2011. View at Publisher · View at Google Scholar
  18. N. Gong, B. Guo, J. Lou, and J. Wang, “Analysis and optimization of leakage current characteristics in sub-65 nm dual Vt footed domino circuits,” Microelectronics Journal, vol. 39, no. 9, pp. 1149–1155, 2008. View at Publisher · View at Google Scholar · View at Scopus
  19. Berkeley Predictive Technology Model (BPTM), http://ptm.asu.edu/.