Design of High-Speed Adders for Efficient Digital Design Blocks

Table 1

Delay, power and area consumed for different adders: a comparision.

Adder	Number of bits	CMOS logic			Transmission gate logic
		Area (no of transistors)	Power in W	Delay in sec	Area (no of transistors)	Power in W	Delay in sec
Kogge-Stone	8	486	4.13 m	2.18𝑒−11	432	1.8799 m	2.33𝑒−10
	16	1140	7.694 m	2.87𝑒−11	1056	5.2718 m	2.38𝑒−10
	32	2658	13.648 m	3.01𝑒−11	2345	10.314 m	2.70𝑒−10
Sklansky	8	415	17.88 m	8.08𝑒−10	323	8.92 m	7.75𝑒−10
	16	1047	36.34 m	11.15𝑒−10	763	18.73 m	10.95𝑒−10
	32	2199	65.13 m	22.03𝑒−10	1659	40.2 m	21.2𝑒−10
Brent-Kung	8	598	0.18 𝜇	7.08𝑒−10	470	0.13 𝜇	7.03𝑒−10
	16	1268	0.4 𝜇	9.24𝑒−10	1012	0.3 𝜇	9.03𝑒−10
	32	2494	12.5 𝜇	11.25𝑒−10	1982	0.614 𝜇	10.4𝑒−10
Han-Carlson	8	440	10.81 m	61.66𝑒−09	312	1.9178 m	60.18𝑒−09
	16	992	13.54 m	82.21𝑒−09	736	6.411 m	81.33𝑒−09
	32	2208	13.99 m	104.8𝑒−09	1696	9.825 m	100.3𝑒−09
Ling	8	742	0.313 𝜇	23.1𝑒−10	530	0.139 𝜇	19.3𝑒−10
	16	1655	0.6 𝜇	35.2𝑒−10	1250	0.3104 𝜇	28.5𝑒−10
	32	3382	13.3 m	42.8𝑒−10	2690	0.4105 𝜇	37.4𝑒−10