A High-Efficient Multi-Output Mixed Dynamic/Static Single-Bit Adder Cell

<table class="table-group" id="tab3"><tr><td><table class="table"><tr><td class="thead-hr" colspan="4"><hr/></td></tr><tr class="thead"><td align="left">Design</td><td align="center">Delay (psec)</td><td align="center">Power (<svg height="12.175" id="M33" style="vertical-align:-3.56265pt" version="1.1" viewbox="0 0 9.5625 12.175" width="9.5625" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,7.675)"><path d="M538 96q-38 -45 -84 -76.5t-71 -31.5q-44 0 -15 117q12 49 18 89h-2q-99 -128 -163 -178q-36 -28 -70 -28q-26 0 -44 38h-2q-16 -69 -16 -129q0 -43 11 -75.5t24 -42.5l1 -6q-7 -12 -24.5 -23t-37.5 -11q-40 0 -40 76q0 52 35 202l94 407l78 24l5 -5q-32 -122 -72 -310
q-7 -33 0 -55t25 -22q36 0 105.5 75t107.5 145l32 146l75 26h10q-50 -197 -78 -347q-7 -38 6 -38q7 0 31 17t47 39z" id="x1D707"></path></g>
</svg>W)</td><td align="center">PDP (aJ)</td></tr><tr><td class="thead-hr" colspan="4"><hr/></td></tr><tr><td align="left">CNFET</td><td align="center">12.980</td><td align="center">5.6878</td><td align="center">7.3827</td></tr><tr><td align="left">MOSFET</td><td align="center">72.924</td><td align="center">8.6618</td><td align="center">63.166</td></tr><tr class="table-tr"><td colspan="4"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

Simulation results for the proposed design (CNFET versus MOSFET technologies).

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tab3

Table 3

Table 3: A High-Efficient Multi-Output Mixed Dynamic/Static Single-Bit Adder Cell 