DFAL: Diode-Free Adiabatic Logic Circuits

<table>Proposed DFAL inverter topology (a) circuit diagram, (b) simulation waveforms using VIRTUOSO SPECTRE simulator of Cadence in 0.18 <i>μ</i>m UMC technology.</table>

International Scholarly Research Notices

fig1

Figure 1

Figure 1: DFAL: Diode-Free Adiabatic Logic Circuits 