Research Article
DFAL: Diode-Free Adiabatic Logic Circuits
Table 2
Comparison of power, delay and PDP with frequency at 20 fF in 10 cycles of charging/discharging.
| Inverters | 1 MHz | 10 MHz | 20 MHz | 33 MHz | 50 MHz | 100 MHz |
| | Power dissipation (W) | |
| CMOS | 0.131 | 0.714 | 1.37 | 2.26 | 3.32 | 6.98 | Proposed | 0.019 | 0.204 | 0.426 | 0.666 | 1.14 | 2.62 |
| | Delay (ns) | |
| CMOS | 0.702 | 0.327 | 0.286 | 0.265 | 0.26 | 0.252 | Proposed | 1.29 | 0.431 | 0.359 | 0.319 | 0.291 | 0.246 |
| | PDP (fJ) | |
| CMOS | 0.092 | 0.23 | 0.39 | 0.6 | 0.86 | 1.76 | Proposed | 0.026 | 0.088 | 0.153 | 0.21 | 0.33 | 0.64 |
| | Energy saving % | |
| | 71.7 | 61.7 | 60.7 | 65 | 61.6 | 63.6 |
| | Adiabatic gain | |
| | 3.54 | 2.61 | 2.54 | 2.86 | 2.6 | 2.75 |
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