Electronically Controllable Sinusoidal Oscillator Employing CMOS VD-DIBAs

Abstract

A new electronically controllable sinusoidal oscillator employing two voltage differencing-differential input buffered amplifiers (VD-DIBAs), two grounded capacitors, and one grounded resistor is presented. The proposed configuration offers (i) independent control of condition of oscillation (CO) and frequency of oscillation (FO) formerly by resistance and later through transconductance, (ii) low active and passive sensitivities, and (iii) a good frequency stability. The workability of the proposed configuration has been demonstrated by SPICE simulation.

1. Introduction

Sinusoidal oscillators find numerous applications in communication, control systems, signal processing, instrumentation, and measurement systems. In the recent past, a large number of single resistance controlled oscillators (SRCOs) have been proposed, see [1–11]; however, in all these SRCOs, the frequency of oscillation can be controlled by varying the values of resistances involved. Obviously, by replacing one of the grounded resistors by JFETs/MOSFETs, electronic tunability can be established, see [2, 4] and the references cited therein. Electronically controllable sinusoidal oscillators (ECSOs) based on different active building blocks are available in the literature, see [12–17] and the references cited therein. The advantages, applications, and usefulness of recently introduced new active building block named voltage differencing-differential input buffered amplifier (VD-DIBA) are now being recognized in the literature [18–20]. Recently, electronically controllable grounded and floating simulated inductance circuits using VD-DIBAs have been introduced in [20]. However, to the best knowledge and belief of the authors, no ECSO using VD-DIBAs has yet been presented in the open literature so far. The purpose of this paper is, therefore, to propose a new ECSO using VD-DIBAs along with a minimum possible number of grounded passive components, which offers (i) independent control of oscillation frequency and condition of oscillation, (ii) low active and passive sensitivities, and (iii) a good frequency stability factor.

2. The Proposed Configuration

The schematic symbol and behavioral model of the VD-DIBA are shown in Figures 1(a) and 1(b), respectively [18]. The model includes two controlled sources: the current source controlled by differential voltage (𝑉₊−𝑉₋), with the transconductance 𝑔_𝑚, and the voltage source controlled by differential voltage (𝑉_𝑧−𝑉_𝑣), with the unity voltage gain. The VD-DIBA can be described by the following set of equations: 𝐼₊𝐼₋𝐼_𝑧𝐼_𝑣𝑉_𝑤=𝑔0000000000_𝑚−𝑔_𝑚𝑉00000000001−10⁺𝑉₋𝑉_𝑧𝑉_𝑣𝐼_𝑤. (1)

(a)

(b)

Figure 1 

(a) Schematic symbol, (b) behavioral model of VD-DIBA.

The proposed new ECSO configuration is shown in Figure 2.

Figure 2 

The proposed configuration.

A routine circuit analysis of Figure 2 yields the following characteristic equation: 𝑠²1+𝑠𝐶₁1𝑅₁−𝑔_𝑚1+𝑔_𝑚1𝑔_𝑚24𝐶₁𝐶₂=0. (2)

Thus, the condition of oscillation (CO) and frequency of oscillation (FO) are given by 1𝑅₁−𝑔_𝑚1𝜔≤0,₀=𝑔_𝑚1𝑔_𝑚24𝐶₁𝐶₂. (3)

Therefore, it is seen that FO is independently controllable by transconductance 𝑔_𝑚2 of the VD-DIBA₂ (which is current controllable by bias current, 𝐼_B2), whereas CO is independently established through the resistor 𝑅₁. The above routine circuit analysis can also be obtained using the analysis performance as given in [21, 22].

The CMOS implementation of VD-DIBA is shown in Figure 3. For this purpose, the TSMC CMOS 0.18 μm process parameters are used for all MOSFETs in the circuit of Figure 3.

Figure 3 

CMOS Implementation of VD-DIBA, 𝑉DD=−𝑉SS=1V,𝐼B1=𝐼B2=𝐼B3=𝐼B4=𝐼B5=𝐼B6=150𝜇A and 𝐼B7=30𝜇𝐴 [20].

Transistor aspect ratios are indicated in Table 1.

Table 1 

The TSMC CMOS 0.18 μm process parameters are given in Table 2.

Table 2 

3. Nonideal Analysis

Let 𝑅_𝑧 and 𝐶_𝑧 denote the parasitic resistance and parasitic capacitance of the 𝑍 terminal. Taking into account the nonidealities of the VD-DIBA, namely 𝑉_𝑤=(𝛽⁺𝑉_𝑧−𝛽⁻𝑉_𝑣), where 𝛽⁺=1−𝜀₁(𝜀₁≪1) and 𝛽⁻=1−𝜀₂(𝜀₂≪1) are voltage tracking errors of the VD-DIBA then the expressions for CO and FO are found to be 𝐶₂+𝐶_𝑍1𝑅₁−𝑔_𝑚1+1𝑅_𝑍𝐶₁+𝐶₂+2𝐶_𝑍𝜔≤0,₀=1/𝑅₁+1/𝑅_𝑍−𝑔_𝑚1𝑅_𝑍+𝛽⁺₂1+𝛽⁻₁−𝛽⁺₁𝑔_𝑚1𝑔_𝑚21+𝛽⁻₂1+𝛽⁻₁𝐶₁𝐶₂. (4)

Taking 𝐶₁=𝐶₂=𝐶≫𝐶_𝑧, and 𝑅_𝑧≫𝑅₁, then (4) reduces to 1𝑅₁−𝑔_𝑚1𝜔≤0,₀=1+𝛽⁻₁−𝛽⁺₁𝛽⁺₂𝑔_𝑚1𝑔_𝑚21+𝛽⁻₁1+𝛽⁻₂𝐶². (5)

This nonideal analysis can also be determined using the analysis performance as given in [23].

The active and passive sensitivities are calculated as 𝑆^𝜔0_𝐶=−1,𝑆^𝜔0_𝛽+1𝛽=−⁺¹21+𝛽⁻₁−𝛽⁺₁,𝑆^𝜔0_𝛽−1=𝛽⁺₁𝛽⁻₁21+𝛽⁻₁−𝛽⁺₁1+𝛽⁻₁,𝑆^𝜔0_𝛽+2=12,𝑆^𝜔0_𝛽−2𝛽=−⁻²21+𝛽⁻₂,𝑆^𝜔0_𝑔𝑚1=12,𝑆^𝜔0_𝑔𝑚2=12, (6) which are all low.

4. Frequency Stability

Using the definition of the frequency stability factor 𝑆^𝐹 as given in [2–4] 𝑆^𝐹=(𝑑𝜙(𝑢)/𝑑𝑢)|_𝑢=1 (where 𝑢=𝜔/𝜔₀ is the normalized frequency and 𝜙(𝑢) represents the phase of the open-loop transfer function of the oscillator circuit), with 𝐶₁=𝐶₂=𝐶, 𝑔_𝑚1=1/𝑅₁=𝑔_𝑚 and 𝑔_𝑚2=𝑛𝑔_𝑚, where 𝑛 is a frequency-controlling transconductor ratio, the 𝑆^𝐹 of the proposed oscillator is found to be √𝑛. Therefore, a good frequency stability is obtainable by selecting larger value of 𝑛.

5. Simulation Results

To verify the theoretical analysis, the proposed circuit has been simulated using the CMOS-based VD-DIBA (Figure 3). The component values used were 𝐶₁=𝐶₂=0.05nF, and 𝑅₁=1.65KΩ, the CMOS VD-DIBA was biased with ±1 V D.C. power supplies with 𝐼_B1=𝐼_B2=𝐼_B3=𝐼_B4=𝐼_B5=𝐼_B6=150𝜇A and 𝐼_B7=30𝜇A. The transconductances of VD-DIBA are controlled by bias currents. SPICE generated output waveforms indicating transient and steady state responses are shown in Figures 4(a) and 4(b), respectively. These results, thus, confirm the validity of the proposed configuration. Figure 5 shows the output spectrum, where the total harmonic distortion (THD) is found to be 1.26%. The oscillator circuit of Figure 2 has been checked for robustness using Monte-Carlo simulations, the sample result has been shown in Figure 6, which confirms that for ±10% variations in the value of 𝑅₁, the value of oscillation frequency remain close to its normal value of 1.005 MHz and hence almost unaffected by change in 𝑅₁. A comparison with other previously known ECSOs has been given in Table 3.

Table 3 

(a)

(b)

Figure 4 

(a) Transient output waveform, (b) steady-state response of the output.

Figure 5 

Simulation result of the output spectrum.

Figure 6 

Result of Monte-Carlo Simulation of oscillator circuit of Figure 2.

6. Concluding Remarks

A new circuit configuration employing two VD-DIBAs along with a minimum possible number of grounded passive elements (i.e., only one resistor and two capacitors) has been proposed. In oscillator mode, the circuit offers (i) independent control of condition of oscillation and frequency of oscillation former by resistance and later through transconductance, (ii) low active and passive sensitivities, and (iii) a good frequency stability for larger values of 𝑛. The validity of the proposed circuit has been established by SPICE simulations.