Abstract
Operational transresistance amplifier (OTRA) has attracted considerable attention in the recent literature in several applications such as impedance simulation, universal biquad filter realization, realization of sinusoidal oscillators and multivibrators. However, to the best knowledge of the authors, any OTRA-based generalized impedance simulator circuits have not been reported so far. The purpose of this paper is to present such a circuit.
1. Introduction
Although a large number of building blocks have been considered as an alternative to the classical voltage-mode operational amplifier (VOA) which suffers from the well-known disadvantage of gain-bandwidth conflict, the OTRA introduced in [1, 2] has been found to be particularly attractive in analog signal processing/signal generation due to the following advantageous features: transmission properties similar to the current feedback op-amp, lack of slew rate limitations as encountered in VOAs, and having two low-impedance inputs and one low-impedance output. The OTRA is a three-terminal analog building block defined by the following matrix equation:
The circuit symbol of the OTRA is shown in Figure 1. In an OTRA, both input terminals are virtually grounded, and the output voltage is the difference between the two input currents multiplied by the transresistance gain , such that
Thus, both input and output terminals are characterized by low impedance, thereby eliminating response limitations incurred by capacitive time constants leading to circuits that are insensitive to the stray capacitances at the input terminals. For ideal operation, the transresistance gain approaches infinity forcing the input currents to be equal. Thus, the OTRA is employed in a negative feedback configuration in a way similar to the operational amplifiers.
For discrete designs, the OTRA can be implemented using two current feedback operational amplifiers (CFOA) (see [3–5], and references cited therein) as shown in Figure 2. On the other hand, from the viewpoint of analog VLSI implementation, several high-performance CMOS OTRA realizations have also been introduced in the current literature for instance, see [1, 6, 7] and the references cited therein. An exemplary CMOS implementation from [6] is shown in Figure 3. The use of OTRAs has been widely investigated in a number of applications such as immitance simulators [3, 5, 8, 9], integrators [10], filters [11–22], square-wave generators [23], current-mode monostable multivibrators [24] and oscillators [4, 25, 26], to name a few.
There have been few earlier attempts on simulating various kinds of impedances using OTRAs for instance, see [3, 5, 8, 9]. In [8], the authors have proposed six circuits for simulating ± parallel with ± and and parallel with ± using single OTRA, under different conditions. In [3], the authors have proposed a circuit for simulating negative inductance with conditions. In [5], the authors have proposed the circuit for simulating ± parallel with using two OTRAs. In [9], two circuits each using two OTRAs along with one capacitor and five resistors are proposed to realize grounded inductors; however, both circuits require fulfilling a condition in terms of four resistors to realize lossless positive inductors. Recently, in [4] the present authors introduced new grounded frequency dependent negative resistance (FDNR) and grounded inductance simulation circuits each employing an operational transresistance amplifier (OTRA) alongwith two capacitors, two resistors and a voltage follower.
The object of this paper is to introduce a new configuration that realizes positive generalized impedance simulator which has wider applications than the circuits reported earlier in [4]. The workability of the proposed circuit has been demonstrated through a number of application examples using discrete as well as CMOS implementations of the OTRAs.
2. The Proposed Generalized Positive Impedance Simulator
The proposed configuration is shown in Figure 4. Assuming the OTRAs to be characterized by the equation , and where is the transresistance gain and considering the OTRAs to be ideal (i.e., ), a routine analysis of the circuit gives the following expression for input impedance:
From (3) it is clear that by appropriate (resistive/capacitive) choice of impedances, the circuit can be easily used to realize an ideal inductor, frequency-dependent-negative resistance (FDNR) having where is known as supercapacitance, resistively-variable capacitance and frequency-dependent negative-capacitance (FDNC) having where is known as super-inductance.
2.1. Grounded Inductor
With the choice of impedance or as a capacitor and the other impedances as resistors, the circuit of Figure 4 can realize a grounded inductor in two ways. (i) with , , , and , the input impedance is given by resulting in a simulated grounded inductor having . (ii) with , , , and , the input impedance is given by and the simulated grounded inductance has a value .
2.2. Grounded FDNR
With any two of the three impedances , and as capacitors, the circuit shown in Figure 4 can realize an FDNR in three ways. (i) with , , , and , the input impedance is found to be and thus, the circuit realizes an ideal grounded FDNR (, where, ). (ii) with , , , and , the input impedance is found to be with and (iii) with , , , and , the input impedance is found to be having .
2.3. Resistively Variable Capacitor
Resistively variable capacitors have several applications in analog circuit design, for instance see [27, 28]. With any one of the three impedances , , and taken as a capacitor, the circuit of Figure 4 realizes a grounded resistively-variable-capacitor in three different ways: (i) with , , , , and , the value of input impedance is found to be , realizing a resistively variable capacitor having (ii) with , , , , and , the input impedance is found to be with , (iii) with , , , , and input impedance is where . It is easy to see that in all cases, can be varied by a single variable resistance.
2.4. Grounded FDNC
With the values of the impedances taken as , , , and , the value of input impedance is found to be . Thus, the circuit of Figure 4 realizes an FDNC whose value is given by .
3. Nonideal Analysis
Practically, the trans-resistance gain of an OTRA is finite and therefore the frequency limitations associated with the OTRA should be considered. Considering a single-pole model, the trans-resistance gain, , can be expressed as
For
where is the DC transresistance gain and is the parasitic capacitance. By straight forward analysis, the general expression for the input impedance of the positive generalized impedance simulator shown in Figure 4 (when the parasitic capacitance of the OTRA is taken into consideration as per (5)) is found to be
Similarly, a still more generalized expression for the input impedance of the positive generalized impedance simulator shown in Figure 4, when the finite output resistance (, typically 15 Ω) and the parasitic capacitance (, typically 5 pF) of the OTRA both were taken into consideration, has been found to be
It is now useful to consider the various special cases. However, to conserve space, we have dealt with only that realization in each case which has been found to be better than the other alternatives.
3.1. Grounded Inductor
With , , , and the expression for the input impedance, considering the non-idealities of OTRA, is found to be
It is obviously not very fruitful to try to make an equivalent nonideal circuit from the above mentioned because it not likely to give any insight about the effect of various parasitic impedances. However, if is represented as , then it would be useful to know the frequency domain behavior of the real and imaginary parts from where we can infer to what extent (in magnitude) and up to what frequency, the non-ideal resistive part, and the inductive part remain close to their intended design values. These plots obtained from SPICE simulations are shown in Figures 5 and 6, respectively, for the circuit designed by taking component values as nF, K, yielding the value of lossless grounded inductor to be mH.
In order to simplify the expression of (8), we consider the following assumptions:
The simplified expression for the input resistance () from (8), after making the previous assumptions, is found to be
can now be expressed in the following form:
where
with
From (13), the appropriate non-ideal value of the inductor simulated by the circuit (at ) is found to be
Thus, it is seen that due to the non-ideal effects, the actual value of the simulated inductor would be slightly more than the intended value. Furthermore, (15) can also be used to obtain a predistorted design of the circuit utilizing known values of and .
From the plots shown in Figures 5 and 6 it is found that the resistive part remains nearly zero ohms as required, showing a value of 14.5 at a frequency of 0.795 MHz and remains very small up to a frequency of about 10 MHz whereas the inductive part shows mH as also predicted by the theoretical formula of (15) which remains almost invariant till a frequency of about 10 MHz. Hence, the usable frequency range of the circuit is till about 10 MHz.
3.2. Grounded FDNR
With , , , and the expression for the input impedance considering the non-idealities of OTRA is found to be
From (16) it can be shown that can be expressed as . From SPICE simulations we have extracted plots showing variation of and as functions of frequency, which are shown respectively in Figures 7 and 8, for component values taken as nF and K, resulting in an ideal value of Ω.
From the plots shown in Figures 7 and 8 it is found that the resistive part remains nearly constant showing a value of Ω (as required) up to a frequency of about 10 MHz whereas the equivalent capacitive value is nF (as also verified by the theoretical formula) which remains almost invariant till a frequency of 10 MHz. Hence, the usable frequency range of the circuit as an FDNR is till about 10 MHz.
3.3. Resistively-Variable Capacitor
With , , , and the expression for the input impedance considering the non-idealities of OTRA was found to be
From (17) it can be shown that can be expressed as . From SPICE simulations we have extracted plots showing variation of and as function of frequency which are shown respectively in Figures 9 and 10, with component values taken as and nF, with ideal value of nF.
From the plots shown in Figures 9 and 10 it is found that the resistive part remains nearly constant showing a value of (which is quite small) up to a frequency of about 10 MHz whereas the equivalent capacitive value is nF (as also verified by the theoretical formula) which remains almost invariant till a frequency of 10 MHz. Hence, the usable frequency range of the circuit is till about 10 MHz.
3.4. Grounded FDNC
With , , , and the expression for the input impedance considering the non-idealities of OTRA was found to be
From (18) it can be shown that can be expressed as . From SPICE simulations we have extracted plots showing variation of and as function of frequency which is shown respectively in Figures 11 and 12, with component values taken as F, KΩ yielding an ideal value of Ω.
From the plots shown in Figures 11 and 12 it is found that the resistive part remains nearly constant showing a value of Ω (which is almost negligible) up to a frequency of about 10 MHz. Hence, the usable frequency range of the circuit is till about 10 MHz.
4. Application Examples
To verify the workability of the proposed structure we now show some sample application circuits and their verification using SPICE simulations.
4.1. Grounded Inductor
With the values of components chosen as nF, KΩ, the simulated lossless grounded inductor has a value of 2.5 mH. The simulated ideal grounded inductor realized using positive generalized impedance simulator circuit shown in Figure 4 is used to design a Second-order band pass filter shown in Figure 13 (having KΩ and pF) for which the transfer function is given by
The circuit realizes a Second-order band pass filter for which the filter parameters are given by: (i) center frequency and (ii) bandwidth . With the choice of impedances as , , , and the input impedance of grounded inductor was found to be resulting in the value of filter parameters as: (i) and (ii) .
A Second-order band pass filter having a center frequency of KHz, MHz and was realized using this inductor by using the component values as nF, KΩ. The OTRA was implemented using AD844 type CFOAs as per the schematic of Figure 2 of [4]. The experimentally observed frequency response is shown in Figure 14 which confirms the workability of the circuit as a band pass filter.
4.2. Grounded FDNR
This was used to realize a Second-order low pass filter consisting of a series RC branch (having and nF) and FDNR (having Ω with the choice of components taken as nF, KΩ, KΩ and KΩ, nF) with the previous values for the FDNR in shunt arm to have a cut-off frequency of . 5886 MHz.
The simulated lossless grounded FDNR was used to design a Second-order low pass filter shown in Figure 15 for which the transfer function is given by
The transfer function thus obtained realizes a Second-order low-pass filter for which the filter parameters are found to be: (i) cut-off frequency and (ii) quality factor . With the choice of impedances as , , , and the input impedance of an ideal grounded FDNR is given by resulting in the value of filter parameters as: (i) and (ii) .
The SPICE generated frequency response using a CMOS implementation of the OTRA (taken from Figure 6 of [6] with 0.5 m CMOS process parameters and aspect ratios of MOSFETs as given in Table 2 therein of [6]) is shown in Figure 16, which confirms the validity of the FDNR realization.
4.3. Resistively-Variable Capacitor
This simulated capacitor was used to realize a variable cut-off frequency first order RC low pass (LP) filter circuit whose cut-off frequency was linearly controlled by varying the resistance . The simulated capacitor realized using positive generalized impedance simulator circuit shown in Figure 4 was used to design a first order low pass filter circuit shown in Figure 17 for which the transfer function is given by
The transfer function thus obtained realizes a first order low pass filter for which the cut-off frequency is . With the choice of impedances as , , , and the input impedance of resistively-variable capacitor gives resulting in the value of filter cut-off frequency as . For values of as 100 Ω, 1 KΩ and 10 KΩ the cut-off frequency is found to be 3.3524 KHz, 23.019 KHz and 188.159 KHz respectively. The simulation results are shown in Figure 18, which therefore confirm the realizability of the resistively variable capacitance.
4.4. Grounded FDNC
The FDNC was tested as a resonator as shown in Figure 19 obtained by shunting it with a resistor resulting in resonant frequency given by . With component values F and KΩ, the SPICE simulation results showed a resonant frequency of 15.625 KHz which is in good agreement with the theoretical value of KHz as shown in Figure 20.
The applications and the simulation results described earlier, thus, confirm the practical validity of the various modes of operation of the proposed configuration.
5. Conclusions
A new generalized positive (it is interesting to point out that a generalized negative impedance simulator using OTRAs can be devised by interchanging the input terminals of OTRA1 and leaving the p-terminal of the same OTRA open with impedance used in the feedback path with impedance connected to the negative terminal. The performance, evaluation, and application of this circuit are, however, a matter of continuing investigations) impedance simulator using OTRAs was presented and its various applications were confirmed by hardware implementation of OTRAs using commercially available AD844-type CFOAs as well as a CMOS implementation of OTRA known earlier.
It is worth pointing out that with CMOS OTRAs and MOS capacitors, the special cases of the proposed configuration can be made completely compatible with CMOS technology by replacing CMOS voltage-controlled resistances (VCRs) in which case, the floating nature of the resistors employed would not create any difficulty since it is well known that grounded and floating VCRs both can be realized with exactly the same number of MOSFETs; for instance, see [29–31].
It is expected that the proposed configuration may find useful applications in the design of analog filters and oscillator design as well as in higher order filter design using methods based upon impedance simulation.
Acknowledgments
This work was performed at Analog Signal Processing Research Lab of the Division of Electronics and Communication Engineering, Netaji Subhas Institute of Technology, New Delhi, India and at Advanced Analog Signal Processing Lab of Department of Electronics and Communication Engineering, Faculty of Engineering and Technology, Jamia Millia Islamia, New Delhi.