Novel Hardware Implementation of the Cipher Message Authentication Code

Table 1

Implementation results for CMAC core.

Device utilization (XC2V1000bg575-5)
Resources	Used	Available	Coverage(%)
CLB Slices	1822	5120	36
BlockRams	10	40	25
Timing report (XC2V1000bg575-5)
Clock frequency (MHz)		159.21
Clock cycle (ns)		6.28
Throughput (Mbps)		1940.90