FPGA Control Implementation of a Grid-Connected Current-Controlled Voltage-Source Inverter
Figure 10
Time domain phase tracking of the grid voltage. In (a), the discrete steps of the PLL output are shown, based on a sampling time of 84 μs, around the zero-crossing of the grid voltage. In (b), 20% Gaussian noise is added to the grid voltage, and the resultant PLL output acts as a lowpass filter.
