FPGA Control Implementation of a Grid-Connected Current-Controlled Voltage-Source Inverter

Table 4

FPGA gate utilization for various implemented functions.

Loop function	Total slices	Slice registers	Slice LUTs	DSP blocks	Block RAM (kbit)	Loop time
abc/ 𝛼𝛽-transform	458	880	851	0	0	9 ticks
𝛼𝛽/dq-transform	476	1010	760	8	0	8 ticks
PLL (without transforms)	1360	2581	3342	4	0	36 𝜇𝑠
Control signal generation	722	1676	1479	15	0	5 ticks
SPWM	541	1,017	1,103	0	0	7 ticks
Overcurrent protection	703	1,009	1,465	1	0	84 𝜇𝑠
Grid monitor with burst log	—	1,375	2,621	1	0.936	84 𝜇𝑠
Gate usage	4,260	9,548	8,279	29	0,936
Gates available	7,200	28,800	28,800	48	1,728
Gate usage (%)	59.16%	33.15%	40.35%	60.42%	54.17%