- About this Journal
- Abstracting and Indexing
- Aims and Scope
- Article Processing Charges
- Articles in Press
- Author Guidelines
- Bibliographic Information
- Citations to this Journal
- Contact Information
- Editorial Board
- Editorial Workflow
- Free eTOC Alerts
- Publication Ethics
- Reviewers Acknowledgment
- Submit a Manuscript
- Subscription Information
- Table of Contents
Journal of Engineering
Volume 2013 (2013), Article ID 626824, 7 pages
Boundary Surface of 5-Valued Memory
Department of Theoretical Electrical Engineering and Electrical Measurement, Technical University of Košice, Park Komenského 3, 040 01 Košice, Slovakia
Received 31 December 2012; Accepted 10 April 2013
Academic Editor: Alfio D. Grasso
Copyright © 2013 Milan Guzan. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
The subject of research in this paper is multiple-valued (MV) memory cell—particularly the morphology of boundary surface of five-valued memory. By accepting the values of parasitic accumulation elements on the chip, very complicated morphology of the boundary surfaces occurs, which separates various attractors from each other. This is due to the occurrence of undesirable oscillations—a stable limit cycles, which makes it impossible to control memory. These dynamic attractors are so dominant that their regions of attraction even surround regions of attraction of static attractors—required logic levels of memory. Therefore, in the realization of the MV memory on the chip is necessary to know the values of the parasitic elements, because their presence may cause a malfunction of the memory. In this case, only calculation and displaying the boundary surface provides exact answers related to operation of the MV memory.
Multiple-valued logic (MVL) compared to the binary logic has the advantage that in circuits with MVL, according to , are reduced the circuits providing transfer into higher orders. Thus, integration density increases and amount of arithmetic operations reduces. This advantage used the Intel corporation for development of MV ROM memory exploited in the coprocessor, but also companies such as NEC, Motorola, General Instruments, and Hitachi used up to 16-value memory .
While in the 80s of the last century MVL memories were designed based on MOS transistors [3–5], in the 90s of the last century they have already dominant resonant tunneling diodes (RTDs) [6–9]. To create elementary MVL memory, only two RTDs are sufficient instead of 6 transistors. This was also one of reasons why RTD broke into the MVL memory design. It should be noted that the use of transistors in the MVL is now up to date  thanks to a new carbon nanotube FETs [11–13]. Other advantages of using RTDs are the ability to work in the GHz region, occupying a tiny area on the chip, the design of multipeak RTD being easy, and having a time-independent I-V characteristic. Change of I-V characteristic of GaAs tunnel diodes due to ageing in the 60s of the last century resulted in malfunction of computers based on these semiconductor devices . Although at 90s of the last century the most publication activity of using RTD in MVL memories was noticed, US patent  proves continued recency of the problems MVL memories based on RTDs. The advantage of using RTDs lies also in the fact that if RTD is characterised by -peaks and both elements are identical, it is possible to create a memory that will be characterised up to stable states—logical levels. So, if , using two RTDs only, it is possible to design such memory which has up to 9 stable states. If we had used MOS transistors, we would have needed greater than 6 MOS transistors.
In order to control any memory, not only just MVL memory, exact investigation of dynamic properties of the elementary memory is necessary. It is not possible without the knowledge of the morphological characteristics of the boundary surface (BS) that separates the regions of attraction of particular attractors. BS is used not only in memories [16–20], but also in chaos generating circuits [21–24]. Therefore, this paper presents morphology of BS in the form of 2D cross-sections for two cases of five-valued elementary memory.
2. MVL Elementary Memory
Circuit of the MV elementary memory is shown in Figure 1. Capacities , include capacity of equivalent RTD circuit or parasitic capacity of the chip. Inductance denotes inductance of leads to diode. Resistance expresses the resistance of conductive connections on the chip. The symbols of nonlinear elements correspond to resonant tunneling diodes. Dependence represents I-V characteristic of element, and dependence represents I-V characteristic of load. Both characteristics are piece-wise linear (PWL) characteristics with indicated break points , , and conductances , , , . Supply voltage mV.
The first ternary memories consisting of RTDs were analyzed in . For mH, μF ternary memory was characterized by three stable states, and memory control by current source was trouble-free. Work  showed that if , , and are comparable with size of parasitic accumulation elements on the chip, a problem may occur. Ternary memory will be characterised not only by three, but four attractors! Newly created attractor is a stable limit cycle (SLC), which disables the memory. Later, two SLCs were found or even three (!) SLCs . Circuit was then characterized by five or even six (!) steady states. Figure 2 illustrates the distribution of singularities in the projection to the , plane and Figure 3 Monge projection of 2D cross-sections of BS through the singularity N1. Symbols S1, S2, and S3 in Figure 2 correspond to stable singularities (attractors) and symbols N1 and N2 to unstable singularities. The same marking is used also in Figure 3.
For a color distinction of particular regions of attraction in Figure 3 the following applies:(i)the green, gray, and red colors represent regions of attraction for stable singularities S1, S2, and S3;(ii)yellow, purple, and blue colors represent regions of attraction of undesired SLCs—L1, L2, and L3.
Marks on SLCs as a cross and dot in a circle represent the intersection of L1, L2, and L3 through corresponding current (plane ) or voltage plane (plane ) . The arrows on SLC illustrate the direction of representative point movement in the state space. Time marks in Figure 3 (projection into plane) illustrate the time interval of representative point movement on SLCs. L1, L2, and L3 are special because they are not tied to an unstable limit cycle as in the cases described in [14, 22, 28, 29]. The symbol denotes absolutely unstable limit cycle. It is absolutely unstable because it lies on the boundary of the four (!) regions of attraction and can be calculated only by backward integration .
The line denoted that EG1 graphically proves if BS is calculated correctly, because element of BS passing through unstable singularity N1 is tangent plane of green and gray regions of attraction just in N1. More information on the elements of singularities can be found in [16, 27, 31]. The presence of the three SLCs in ternary memory is interesting in terms of the theory of nonlinear circuits, but in terms of implementation of the memory, SLCs represent a warning. But it is possible to find such parameters , , and , when SLCs are not present and memory can be realised . The author of this paper is interested in BS morphology for five-valued elementary memory. A sure thing should be five attractors—logic states of elementary memory. However, the question is whether they will again present undesirable SLCs also in structures described in the next section, where , , and will be comparable with parasitic values on the chip.
3. Five-Valued Memory
Circuit in Figure 1, as for ternary memory even for five-valued memory, is described by system
The expressions (2) and (3) from work  have been modified to express the PWL and characteristics, to form where are conductances and are the break points I-V characteristics. If , it concerned load, if , it concerned active device.
Expression (2) and parameters (4) or expression (3) and parameters (5) correspond to such I-V characteristics in order to achieve five stable singularities S1, S2, S3, S4, and S5. As is clear from Figure 4(a), both I-V characteristics are identical—defined by the relation (2). Since one RTD is active device and the second is load, it is possible to make 5 stable singularities. A similar comment applies to Figure 5(a), with the difference that the active and the load device are defined by the relation (3). To parameters (4) corresponds Figure 4(a) and to parameters (5) corresponds Figure 5(a). From both projections to the plane is obvious active and load device. Singularities N1, N2, N3, and N4 regularly separate stable singularity from each other, where When , the number of singularities of the system (1) and their coordinates is given by the system of algebraic equations
As in the case of ternary memory , control cross-sections of BS were made through unstable singularities by the grid method (Figures 4(b) and 5(b)). The grid method was first used in , and its principle is based on the following procedure. Cutting plane of BS is divided into points—the initial conditions of solution of system (1) by the Runge-Kutta method. Each one representative point is attracted by some of the attractors. The result is then a 2D cross-section of BS where you can see the size of the regions of attraction corresponding to individual attractors in the circuit. Color figures in this paper, illustrating BS cross-sections, consist of points. One figure, therefore, consists of 193 600 points.
Since all unstable singularities for the RTD parameters (4) have the same current coordinate, (Figure 4(b)) the cross-section of the BS was calculated and displayed for mA. This image is a color key to Figure 6. Since , projection of intersections I-V surfaces with the plane , is line. The symbol () on the line indicates stable singularities S1–S5 and symbol (+) unstable singularities N1–N4. The fact, that N1–N4 lie exactly on the boundary of color regions proves that the cross-section of BS is calculated correctly. Designation S1–S5 is located in the color region corresponding to the region of attraction of incident attractor. Surprising finding was that the memory was characterized by another 10 (!) SLCs.
They are labeled as L1–L10, and colored regions are symmetrically distributed around the linear projection of I-V surfaces. For example, the region of the attraction of SLC L1 is marked by yellow. In one of the two yellow regions, you can find label L1. SLC L2 is marked by light green color labeled L2 (dark green color corresponds to the region of attraction for attractor S2). Last SLC-L10 in Figure 4(b) is marked by white color. Because of the symmetry of I-V characteristics and uniform spacing of singularities, BS cross-section in Figure 4(b) evokes a chessboard. This implies relatively the same size of the regions of attraction as for S1–S5, as well as for L1–L10. Since the presence of up to 10 SLCs was surprising for the author, he proposed hypothetical parameters of RTD (5). These parameters would be difficult to realize, but for verification, BS morphology of other five-valued memory is sufficient. Because the distribution of singularities is not as uniform as in the previous case, Figure 5(b) is not characterised by approximately equal regions of attraction as shown in the Figure 4(b). Cross-section of BS was realised through current level mA, which is current level corresponding to unstable singularities N2 and N3. Symbols of labelling S1–S5 and N1–N4 and principles of SLC marking L1–L8 are the same as in the commentary to Figure 4(b). Although this structure contains 8 SLCs, the presence of even a single SLC memory makes this MV memory unusable.
BS morphology of both cases is shown in Figures 6 and 7 in the plane , . The key to the location of singularities and the color regions of attraction is Figures 4(b) and 5(b) to Figures 6 and 7, respectively. The number placed at the top of the figure indicates the current in mA. Labels N2, N3, or N1, N4 instead of number labels in Figure 7 indicates, that the cross-sections of BS correspond to current levels of unstable singularities N2, N3, or N1, N4. These are listed in the figure caption. If we compare Figures 6 and 7, we can conclude that the BS morphology is quite complicated. At low or high current levels are dominant regions of attraction for SLC. Regions of attraction for S1–S5 are actually “encapsulated” by regions of attraction for SLC and in 3D state space form objects like “cones.”
Since the change of , , and can significantly affect the functionality of the newly designed prospective memory, it is almost a necessity to know the morphology of BS. Without its knowledge, it is very difficult to find the optimal parameters of the control pulse. Otherwise, the designer of memory is forced to use inefficient method of “trial-error” that does not explain the failure of memory, for example, due to the presence of SLCs. The possibility of practical utilization of SLCs, occurring in memories, is unknown to the author. Therefore, he evaluates negatively their presence in memory structures. Given that in the ternary memory such parameters , , and were found, leading to the extinction of SLCs, it can be assumed that even in five-valued memory the same analogy would be possible. Then, BS morphology would be much easier. Presence of virtual saddle singularity, or cases of very complex BS morphology can even happen . Mentioned cases make control memory impossible, despite the absence of SLC. Even under these notes, the knowledge of BS morphology is important part in the analysis of MV memories. Other activities for examining the points mentioned earlier will continue if author will meet the interest in science public.
This work is the result of the project implementation: KEGA no. 005TUKE-4/2012—“Automated checking system based on modern information technology.”
- J. T. Butler, “Multiple-valued logic,” IEEE Potentials, vol. 14, no. 2, pp. 11–14, 1995.
- M. Kameyama, “Multiple-valued logic TC stresses innovation,” Computer, vol. 30, no. 5, pp. 83–85, 1997.
- P. C. Balla and A. Antoniou, “Low power dissipation MOS ternary logic family,” IEEE Journal of Solid-State Circuits, vol. 19, no. 5, pp. 739–749, 1984.
- A. Heung and H. T. Mouftah, “Depletion/enhancement CMOS for a low power family of three-valued logic circuits,” IEEE Journal of Solid-State Circuits, vol. 20, no. 2, pp. 609–616, 1985.
- Y. Yasuda, Y. Tokuda, S. Zaima, K. Pak, T. Nakamura, and A. Yoshida, “Realization of quaternary logic circuits by n-channel MOS devices,” IEEE Journal of Solid-State Circuits, vol. 21, no. 1, pp. 162–168, 1986.
- A. A. Lakhani and R. C. Potter, “Combining resonant tunneling diodes for signal processing and multilevel logic,” Applied Physics Letters, vol. 52, no. 20, pp. 1684–1685, 1988.
- F. Capasso, S. Sen, F. Beltram et al., “Quantum functional devices: resonant-tunneling transistors, circuits with reduced complexity, and multiple valued logic,” IEEE Transactions on Electron Devices, vol. 36, no. 10, pp. 2065–2082, 1989.
- A. C. Seabaugh, Y. C. Kao, and H. T. Yuan, “Nine-state resonant tunneling diode memory,” IEEE Electron Device Letters, vol. 13, no. 9, pp. 479–481, 1992.
- T. Waho, K. J. Chen, and M. Yamamoto, “A novel multiple-valued logic gate using resonant tunneling devices,” IEEE Electron Device Letters, vol. 17, no. 5, pp. 223–225, 1996.
- R. Cunha, H. Boudinov, and L. Carro, “Quaternary look-up tables using voltage-mode CMOS logic design,” in Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL '07), p. 56, May 2007.
- A. Raychowdhury and K. Roy, “Carbon-nanotube-based voltage-mode multiple-valued logic design,” IEEE Transactions on Nanotechnology, vol. 4, no. 2, pp. 168–179, 2005.
- H. Nan and K. Choi, “Novel ternary logic design based on CNFET,” in Proceedings of the International SoC Design Conference (ISOCC '10), pp. 115–118, November 2010.
- S. Lin, Y. B. Kim, and F. Lombardi, “A novel CNTFET-based ternary logic gate design,” in Proceedings of the 52nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS '09), pp. 435–438, August 2009.
- V. Špány, “Multistable systems and special surfaces m-dimensional state space,” Elektrotechnický Časopis, vol. 33, no. 7, pp. 551–556, 1982 (Slovak).
- R. Vega and S. Sudirgo, “Multi-valued logic/memory cells and methods thereof,” US Patent No. 7548455B2, June 2009.
- M. Guzan, “Boundary surface and tangential plane in multiple-valued memory,” in Proceedings of the International Conference of Teachers of Electrical Engineering (SEKEL '10), pp. 62–67, 2010.
- P. Galajda, M. Guzan, and V. Špány, “The state space description of the MVL memory circuits,” in Proceedings of the International Conference Education, Science and Economics at Universities: Integration to International Educational AREA, pp. 351–359, Plock, Poland, 2010.
- P. Galajda, V. Špány, and M. Guzan, “The state space mystery with virtual saddle point in memory cell,” in Proceedings of the 6th International Conference on Digital Signal Processing and Multimedia Communications (DSP-MCOM '05), pp. 147–150, Kosice, Slovakia, 2005.
- M. Guzan, “Boundary surface of a ternary memory in the absence of limit cycles,” in Proceedings of the 22nd International Conference Radioelektronika, pp. 1–4, 2012.
- M. Guzan and B. Sobota, “Boundary surface of multiple-valued memory in 3D,” in Proceedings of the International Conference of Teachers of Electrical Engineering (SEKEL '12), pp. 75–80, 2012.
- V. Špány and L. Pivka, “Boundary surfaces in sequential circuits,” International Journal of Circuit Theory and Applications, vol. 18, no. 4, pp. 349–360, 1990.
- L. Pivka and V. Špány, “Boundary surfaces and basin bifurcations in Chua's circuit,” Journal of Circuits, Systems and Computers, vol. 3, no. 2, pp. 441–470, 1993.
- B. Sobota, “3D modelling of Chua's circuit boundary surface,” Acta Electrotechnica et Informatica, vol. 11, no. 1, pp. 44–47, 2011.
- V. Špány, P. Galajda, M. Guzan, L. Pivka, and M. Olejár, “Chua's singularities: great miracle in circuit theory,” International Journal of Bifurcation and Chaos, vol. 20, no. 10, pp. 2993–3006, 2010.
- P. Galajda, The analysis of the multiple-valued memory cell [Ph.D. thesis], 1995.
- P. Galajda, M. Guzan, and V. Špány, “Boundary surfaces of one port memories,” in Proceedings of the 5th International Conference Tesla Millenium, pp. 131–137, 1996.
- P. Galajda, M. Guzan, and V. Špány, “The state space mystery with negative load,” Radioengineering, vol. 8, no. 2, pp. 2–7, 1999.
- T. E. Stern, Theory of Nonlinear Networks and Systems, 1965.
- V. Špány, “Special surfaces and trajectories of the multidimensional state space,” in Proceedings of the Scientific Works of TU of Kosice, pp. 123–152, 1978.
- M. Guzan, “Boundary surface and limit cycles of ternary memory by using forward and backward integration,” in Proceedings of the 17th International Conference on Electrical Drives and Power Electronics (EDPE '11) and proceedings of the 5th Joint Slovak-Croatian Conference, pp. 171–175, Košice, Slovakia, September 2011.
- M. Guzan, P. Galajda, L. Pivka, and V. Špány, “Element of singularity is a key to laws of chaos,” in Proceedings of the 15th International Czech-Slovak Scientific Conference (Radioelektronika '05), pp. 33–36, University of Technology, Brno, Czech Republic, 2005.
- V. Špány, “The expression of the non-linear characteristics by means of absolutes values,” Slaboproudý Obzor, vol. 40, no. 7, pp. 354–356, 1988 (Slovak).