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Journal of Engineering
Volume 2013 (2013), Article ID 626824, 7 pages
http://dx.doi.org/10.1155/2013/626824
Research Article

Boundary Surface of 5-Valued Memory

Department of Theoretical Electrical Engineering and Electrical Measurement, Technical University of Košice, Park Komenského 3, 040 01 Košice, Slovakia

Received 31 December 2012; Accepted 10 April 2013

Academic Editor: Alfio D. Grasso

Copyright © 2013 Milan Guzan. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The subject of research in this paper is multiple-valued (MV) memory cell—particularly the morphology of boundary surface of five-valued memory. By accepting the values of parasitic accumulation elements on the chip, very complicated morphology of the boundary surfaces occurs, which separates various attractors from each other. This is due to the occurrence of undesirable oscillations—a stable limit cycles, which makes it impossible to control memory. These dynamic attractors are so dominant that their regions of attraction even surround regions of attraction of static attractors—required logic levels of memory. Therefore, in the realization of the MV memory on the chip is necessary to know the values of the parasitic elements, because their presence may cause a malfunction of the memory. In this case, only calculation and displaying the boundary surface provides exact answers related to operation of the MV memory.