A Very Compact AES-SPIHT Selective Encryption Computer Architecture Design with Improved S-Box

Table 7

Gate counts on ALU components.

ALU Block	AND	XOR/XNOR	OR
Adder (10-bit)	20	20	10
XOR (8-bit)	—	8	—
𝑥time	—	8	—
*SubBytes (dual-inverse affine, straight line circuit)	32	111	—
**SubBytes	32	97	—

*: The proposed S-box with dual-inverse affine, a straight line circuit (refer to Figures 10 and 11).
**: The proposed S-box using methodology 1 and 2 (Sections 3.2 and 3.3).