A Very Compact AES-SPIHT Selective Encryption Computer Architecture Design with Improved S-Box

<table class="table-group" id="tab9"><tr><td><table class="table"><tr><td class="thead-hr" colspan="3"><hr/></td></tr><tr class="thead"><td align="left">Designs</td><td align="center">Ours</td><td align="center">
									Good and Benaissa [<a href="/journals/je/2013/785126/#B30">27</a>]</td></tr><tr><td class="thead-hr" colspan="3"><hr/></td></tr><tr><td align="left">Instruction set count</td><td align="center">4</td><td align="center">14</td></tr><tr class="table-tr"><td colspan="3"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

Comparisons with other small AES processors.

Journal of Engineering

tab9

Table 9

Table 9: A Very Compact AES-SPIHT Selective Encryption Computer Architecture Design with Improved S-Box 