Chip-Level HARQ Chase Combining for HSUPA

<table class="table-group" id="tab1"><tr><td><table class="table"><tr><td class="thead-hr" colspan="6"><hr/></td></tr><tr class="thead"><td align="left">MCS</td><td align="center">Number of codes</td><td align="center">Min SF</td><td align="center">Coding rate</td><td align="center">Modulation</td><td align="center">Max. bit rate (kbps)</td></tr><tr><td class="thead-hr" colspan="6"><hr/></td></tr><tr><td align="left">1</td><td align="center">4</td><td align="center">2</td><td align="center">0.703</td><td align="center">BPSK</td><td align="center">4050.0</td></tr><tr><td align="left">2</td><td align="center">4</td><td align="center">2</td><td align="center">0.704</td><td align="center">16-QAM</td><td align="center">8109.0</td></tr><tr class="table-tr"><td colspan="6"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

Journal of Electrical and Computer Engineering

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Table 1

Table 1: Chip-Level HARQ Chase Combining for HSUPA 