Journal of Electrical and Computer Engineering
Volume 2011 (2011), Article ID 361384, 10 pages
doi:10.1155/2011/361384
Research Article

Differential Difference Current Conveyor Transconductance Amplifier: A New Analog Building Block for Signal Processing

Neeta Pandey1 and Sajal K. Paul2

1Department of Electronics and Communication Engineering, Delhi Technological University, Delhi 110042, India
2Department of Electronics Engineering, Indian School of Mines, Jharkhand 826004, India

Received 30 March 2011; Revised 28 August 2011; Accepted 31 August 2011

Academic Editor: Raj Senani

Copyright © 2011 Neeta Pandey and Sajal K. Paul. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

A new active building block for analog signal processing, namely, differential difference current conveyor transconductance amplifier (DDCCTA), is presented, and performance is checked through PSPICE simulations which show the usability of the proposed element is up to 201 MHz. The proposed block is implemented using 0.25 μm TSMC CMOS technology. Some of the applications are presented using the proposed DDCCTA, namely, a voltage mode multifunction filter, a current mode universal filter, an oscillator, current and voltage amplifiers, and grounded inductor simulator. The feasibility of DDCCTA and its applications is confirmed via PSPICE simulations.

1. Introduction

The analog integrated circuit design in current mode is receiving increased attention due to some potential performance features like wide bandwidth, less circuit complexity, wide dynamic range, low power consumption, and high operating speed [1]. The current mode approach has emerged as an alternate method besides the traditional voltage mode circuits. The current mode active elements are appropriate to operate with signals in current or voltage or mixed mode and are gaining acceptance as building blocks in high-performance circuit designs. A number of current mode active elements such as operational transconductance amplifier (OTA) [2], current conveyors (CCs) [3–5], differential voltage current conveyor (DVCC) [6], differential difference current conveyor (DDCC) [7], current feedback operational amplifier (CFOA) [8] are available in the literature.

Recently some new analog building blocks, such as current conveyor transconductance amplifier (CCTA) [9, 10], current controlled current conveyor transconductance amplifier (CCCCTA) [11], current difference transconductance amplifier (CDTA) [12], current controlled current difference transconductance amplifier (CCCDTA) [13], differential voltage current conveyor transconductance amplifier (DVCCTA) [14], and differential voltage current controlled conveyor transconductance amplifier (DVCCCTA) [15], are reported in the literature. These may be constructed by cascading of current mode building blocks with transconductance amplifier (TA) analog building blocks in monolithic chip for compact implementation of signal processing circuits and systems. It is well known that DDCC has some advantages [7, 16, 17] specially for applications demanding differential and floating inputs, over CCII or CCCII owing to three high input impedance terminals for DDCC compared to one high input impedance terminal for CCII or CCCII. However, DDCC does not have a powerful inbuilt tuning property in contrast to CCCII. The DDCC is more versatile than DVCC as it has an extra high input impedance terminal.

The main intention of this paper is to propose a new active building block, namely, differential difference current conveyor transconductance amplifier (DDCCTA), which has DDCC [7] as input block and is followed by a TA. The DDCCTA has all the good properties of CCTA, CCCCTA, and DVCCTA including the possibility of inbuilt tuning of the parameters of the signal processing circuits to be implemented and also all the versatile and special properties of DDCC such as easy implementation of differential and floating input circuits. However, the same may be implemented using separate DDCC and OTA analog building blocks, but it will be more convenient and useful if DDCCTA is implemented in monolithic chip which will result in compact implementation of signal processing circuits and systems. Section 2 deals with the proposed DDCCTA circuit and some of its properties. Section 3 is devoted for some of its applications in developing signal processing circuits such as voltage mode (VM) filter, current mode (CM) filter, oscillator, current and voltage amplifier, and grounded inductor simulator. The functionality of all the proposed circuits has been verified using SPICE simulations. The conclusion is given in Section 4.

2. Proposed DDCCTA

The DDCCTA is based on DDCC [7] and consists of differential amplifier, current mirrors, and TA. The port relationships of the DDCCTA as shown in Figure 1 can be characterized by the following matrix: ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ 𝐼 𝑌 1 𝐼 𝑌 2 𝐼 𝑌 3 𝑉 𝑋 𝐼 𝑍 1 + 𝐼 𝑍 2 + 𝐼 0 1 − 𝐼 𝑂 2 − ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ = ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 − 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 − 𝑔 𝑚 0 0 0 0 0 0 0 − 𝑔 𝑚 ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ × ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ 𝑉 0 0 0 𝑌 1 𝑉 𝑌 2 𝑉 𝑌 3 𝐼 𝑋 𝑉 𝑍 1 + 𝑉 𝑍 2 + 𝑉 𝑂 1 − 𝑉 𝑂 2 − ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ , ( 1 ) where 𝑔 𝑚 is transcon/ductance of the DDCCTA.

361384.fig.001
Figure 1: Circuit symbol of the proposed DDCCTA.

The CMOS-based internal circuit of DDCCTA in CMOS is depicted in Figure 2. It consists of the circuit of DDCC [7] (transistors M1 to M14) followed by a transconductance amplifier (transistors M15 to M24). The derivation of port relationships is given in Sections 2.1 to 2.3 [13].

361384.fig.002
Figure 2: DDCCTA implementation.
2.1. Relationship between Voltages of 𝑋 Port and 𝑌 1 , 𝑌 2 , and 𝑌 3 Ports

The voltage at 𝑋 port may be found by analyzing the differential difference part (comprising of transistors M1 to M10) of the circuit of Figure 2 as follows: 𝑉 𝑋 = 𝛽 1 𝑉 𝑌 1 − 𝛽 2 𝑉 𝑌 2 + 𝛽 𝑉 𝑌 3 + 𝜀 𝑉 , ( 2 ) where 𝛽 1 = 1 𝑃 1 𝑔 𝑚 3 𝑔 𝑚 6 + 𝑔 𝑚 3 𝑔 𝑚 4 𝑔 𝑚 5 − 𝑔 𝑚 3 𝑔 𝑚 6 𝑔 𝑚 3 + 𝑔 𝑚 4 , 𝛽 2 = 1 𝑃 1 𝑔 𝑚 1 𝑔 𝑚 5 + 𝑔 𝑚 1 𝑔 𝑚 1 𝑔 𝑚 5 − 𝑔 𝑚 2 𝑔 𝑚 6 𝑔 𝑚 1 + 𝑔 𝑚 2 , 𝛽 3 = 1 𝑃 1 𝑔 𝑚 2 𝑔 𝑚 6 + 𝑔 𝑚 2 𝑔 𝑚 1 𝑔 𝑚 5 − 𝑔 𝑚 2 𝑔 𝑚 6 𝑔 𝑚 1 + 𝑔 𝑚 2 , 𝜀 𝑉 𝐼 = − 𝐵 𝑃 1 𝑔 𝑚 1 𝑔 𝑚 5 − 𝑔 𝑚 2 𝑔 𝑚 6 𝑔 𝑚 1 + 𝑔 𝑚 2 + 𝑔 𝑚 4 𝑔 𝑚 5 − 𝑔 𝑚 3 𝑔 𝑚 6 𝑔 𝑚 3 + 𝑔 𝑚 4 , 𝑃 1 = 𝑔 𝑚 4 𝑔 𝑚 5 − 𝑔 𝑚 4 𝑔 𝑚 4 𝑔 𝑚 5 − 𝑔 𝑚 3 𝑔 𝑚 6 𝑔 𝑚 3 + 𝑔 𝑚 4 , ( 3 ) and 𝐼 𝐵 represents current through transistor Mi ( 𝑖 = 7 , 8 , 1 0 , 1 2 , 1 4 ). With matched transconductances 𝑔 𝑚 1 = 𝑔 𝑚 2 = 𝑔 𝑚 3 = 𝑔 𝑚 4 and 𝑔 𝑚 5 = 𝑔 𝑚 6 , 𝑉 𝑋 is obtained as 𝑉 𝑋 = 𝑉 𝑌 1 − 𝑉 𝑌 2 + 𝑉 𝑌 3 . ( 4 )

2.2. Relationship between Currents at 𝑍 1 + , 𝑍 2 + , and 𝑋 Ports

The analysis of the portion of the circuit comprising of transistors M9 to M14 of the circuit of Figure 2 gives 𝐼 𝑍 1 + = 𝛼 1 𝐼 𝑋 + 𝜀 𝐼 1 , 𝐼 𝑍 2 + = 𝛼 2 𝐼 𝑋 + 𝜀 𝐼 2 , ( 5 ) where 𝛼 1 = 𝑔 𝑚 1 1 𝑔 𝑚 9 , 𝜀 𝐼 1 = 𝑔 1 − 𝑚 1 1 𝑔 𝑚 9 𝐼 𝐵 , 𝛼 2 = 𝑔 𝑚 1 3 𝑔 𝑚 9 , 𝜀 𝐼 2 = 𝑔 1 − 𝑚 1 3 𝑔 𝑚 9 𝐼 𝐵 . ( 6 ) For matched transconductances 𝑔 𝑚 9 = 𝑔 𝑚 1 1 = 𝑔 𝑚 1 3 , the port currents are simplified to 𝐼 𝑍 1 + = 𝐼 𝑍 2 + = 𝐼 𝑋 . ( 7 )

2.3. Relation for Currents at 𝑂 1 − and 𝑂 2 − Ports

The proposed DDCCTA contains a transconductor cell comprising of transistors M15 to M24. Assuming gate voltages of transistors M17 and M18 as 𝑉 𝑇 1 and 𝑉 𝑇 2 , the output currents 𝐼 𝑂 1 − and 𝐼 𝑂 2 − may be found, respectively, as 𝐼 𝑂 1 − 𝛾 = − 1 𝑉 𝑇 1 − 𝛾 2 𝑉 𝑇 2 + 𝜀 𝑇 1 , 𝐼 𝑂 2 − 𝛾 = − 3 𝑉 𝑇 1 − 𝛾 4 𝑉 𝑇 2 + 𝜀 𝑇 2 , ( 8 ) where 𝛾 1 = 𝑔 𝑚 1 7 𝑔 𝑚 1 6 𝑔 𝑚 2 2 𝑔 𝑚 1 5 𝑔 𝑚 2 1 − 1 𝑔 𝑚 1 5 𝑔 𝑚 1 9 𝑔 𝑚 2 1 × 𝑔 𝑚 1 6 𝑔 𝑚 1 7 𝑔 𝑚 1 9 𝑔 𝑚 2 2 − 𝑔 𝑚 1 5 𝑔 𝑚 1 8 𝑔 𝑚 2 0 𝑔 𝑚 2 1 𝑔 𝑚 1 7 + 𝑔 𝑚 1 8 , 𝛾 2 = 𝑔 𝑚 1 8 𝑔 𝑚 2 0 𝑔 𝑚 1 9 + 1 𝑔 𝑚 1 5 𝑔 𝑚 1 9 𝑔 𝑚 2 1 × 𝑔 𝑚 1 6 𝑔 𝑚 1 7 𝑔 𝑚 1 9 𝑔 𝑚 2 2 − 𝑔 𝑚 1 5 𝑔 𝑚 1 8 𝑔 𝑚 2 0 𝑔 𝑚 2 1 𝑔 𝑚 1 7 + 𝑔 𝑚 1 8 , 𝛾 3 = 𝑔 𝑚 1 7 𝑔 𝑚 1 6 𝑔 𝑚 2 4 𝑔 𝑚 1 5 𝑔 𝑚 2 1 − 1 𝑔 𝑚 1 5 𝑔 𝑚 1 9 𝑔 𝑚 2 1 × 𝑔 𝑚 1 6 𝑔 𝑚 1 7 𝑔 𝑚 1 9 𝑔 𝑚 2 4 − 𝑔 𝑚 1 5 𝑔 𝑚 1 8 𝑔 𝑚 2 3 𝑔 𝑚 2 1 𝑔 𝑚 1 7 + 𝑔 𝑚 1 8 , 𝛾 4 = 𝑔 𝑚 1 8 𝑔 𝑚 2 3 𝑔 𝑚 1 9 + 1 𝑔 𝑚 1 5 𝑔 𝑚 1 9 𝑔 𝑚 2 1 × 𝑔 𝑚 1 6 𝑔 𝑚 1 7 𝑔 𝑚 1 9 𝑔 𝑚 2 4 − 𝑔 𝑚 1 5 𝑔 𝑚 1 8 𝑔 𝑚 2 3 𝑔 𝑚 2 1 𝑔 𝑚 1 7 + 𝑔 𝑚 1 8 , 𝜀 𝑇 1 𝐼 = − B i a s 𝑔 𝑚 1 5 𝑔 𝑚 1 9 𝑔 𝑚 2 1 × 𝑔 𝑚 1 6 𝑔 𝑚 1 7 𝑔 𝑚 1 9 𝑔 𝑚 2 2 − 𝑔 𝑚 1 5 𝑔 𝑚 1 8 𝑔 𝑚 2 0 𝑔 𝑚 2 1 𝑔 𝑚 1 7 + 𝑔 𝑚 1 8 , 𝜀 𝑇 2 𝐼 = − B i a s 𝑔 𝑚 1 5 𝑔 𝑚 1 9 𝑔 𝑚 2 1 × 𝑔 𝑚 1 6 𝑔 𝑚 1 7 𝑔 𝑚 1 9 𝑔 𝑚 2 4 − 𝑔 𝑚 1 5 𝑔 𝑚 1 8 𝑔 𝑚 2 3 𝑔 𝑚 2 1 𝑔 𝑚 1 7 + 𝑔 𝑚 1 8 . ( 9 ) With 𝑔 𝑚 1 7 = 𝑔 𝑚 1 8 , 𝑔 𝑚 2 1 = 𝑔 𝑚 2 2 = 𝑔 𝑚 2 4 , 𝑔 𝑚 1 5 = 𝑔 𝑚 1 6 = 𝑔 𝑚 1 9 = 𝑔 𝑚 2 0 = 𝑔 𝑚 2 3 , the output currents 𝐼 𝑂 1 − and 𝐼 𝑂 2 − reduce to 𝐼 𝑂 1 − 𝑔 = − 𝑚 1 7 𝑉 𝑇 1 − 𝑔 𝑚 1 8 𝑉 𝑇 2 𝐼 , ( 1 0 ) 𝑂 2 − 𝑔 = − 𝑚 1 7 𝑉 𝑇 1 − 𝑔 𝑚 1 8 𝑉 𝑇 2 . ( 1 1 ) In the circuit, 𝑉 𝑇 1 = 𝑉 𝑍 1 + and 𝑉 𝑇 2 = 0 ; hence the output currents are simplified to 𝐼 𝑂 1 − = − 𝑔 𝑚 1 7 𝑉 𝑍 1 + , 𝐼 𝑂 2 − = − 𝑔 𝑚 1 7 𝑉 𝑍 1 + . ( 1 2 )

The value of 𝑔 𝑚 1 7 is obtained as √ 2 𝜇 𝐶 o x ( 𝑊 / 𝐿 ) 1 7 𝐼 B i a s if transistors are biased in strong inversion region and 2 𝐼 B i a s / 𝑉 𝑇 ( 𝑉 𝑇 = 𝐾 𝑇 / 𝑞 ) if transistors are biased in subthreshold region which can be adjusted by bias current 𝐼 B i a s .

2.4. Simulation

To validate the behaviour of the proposed element, PSPICE simulations have been carried out using TSMC 0.25 μm CMOS process model parameters. The supply voltages of 𝑉 D D = − 𝑉 S S = 1 . 2 5  V and 𝑉 B B = − 0 . 8  V are used. The aspect ratio of various transistors for DDCCTA is given in Table 1. The DC transfer characteristics of the proposed DDCCTA from 𝑌 1 , 𝑌 2 , and 𝑌 3 terminals to 𝑋 terminal are shown in the Figure 3. It is clear that the voltage at 𝑋 terminal follows the 𝑌 terminal voltages in the range of −200 mV to +200 mV. The variation of current at 𝑍 1 + and 𝑍 2 + terminals with 𝑋 terminal current from −100 μA to 100 μA is shown in Figure 4. It may be noted that there is deviation for current below −80 μA. The variation of the transconductance value by changing 𝐼 B i a s from 0 to 500 μA is depicted in Figure 5. The decreases in transconductance for larger bias currents than 450 μA or so is due to transistors (M17, M18) entering in linear region of operation from saturation region. The maximum transconductance is about 1.6 mS. The other circuit performance parameters of the DDCCTA are summarised in Table 2.

tab1
Table 1: Aspect ratio of various transistors.
tab2
Table 2: Circuit performance parameters of the DDCCTA.
fig3
Figure 3: DC transfer characteristic for voltage transfer from (a) 𝑌 1 port to 𝑋 port, (b) 𝑌 2 port to 𝑋 port, and (c) 𝑌 3 port to 𝑋 port.
361384.fig.004
Figure 4: DC transfer characteristic for current transfer from 𝑋 port to 𝑍 1+ and 𝑍 2+ ports.
361384.fig.005
Figure 5: Variation of transconductance with bias current.

3. Applications

3.1. Multifunction Voltage Mode Filter

In this section a multifunction voltage mode (VM) filter is proposed. It uses a single DDCCTA, two grounded capacitors, and a grounded resistor. The proposed multifunction VM filter is shown in Figure 6. The analysis of circuit yields the output voltages at various nodes as 𝑉 o u t 1 𝑉 i n = 𝑠 2 𝐶 1 𝐶 2 𝑅 , 𝑉 𝐷 ( 𝑠 ) o u t 2 𝑉 i n = 𝑠 𝐶 2 𝐷 , 𝑉 ( 𝑠 ) o u t 3 𝑉 i n 𝑔 = − 𝑚 , 𝐷 ( 𝑠 ) ( 1 3 ) where 𝐷 ( 𝑠 ) = 𝑠 2 𝐶 1 𝐶 2 𝑅 + 𝑠 𝐶 2 + 𝑔 𝑚 . ( 1 4 )

361384.fig.006
Figure 6: Proposed voltage mode filter.

It may be observed from (13) that high-pass, band-pass, and low-pass responses are available simultaneously at 𝑉 o u t 1 , 𝑉 o u t 2 , and 𝑉 o u t 3 , respectively. Thus, the proposed structure is a single-input-and-three-output voltage mode filter. It may be noted that no component matching constraint is required. The responses are characterized by pole frequency ( 𝜔 0 ), bandwidth ( 𝜔 0 / 𝑄 0 ), and quality factor ( 𝑄 0 ) as 𝜔 0 = 𝑔 𝑚 𝑅 𝐶 1 𝐶 2 1 / 2 , 𝜔 0 𝑄 0 = 1 𝑅 𝐶 1 , 𝑄 0 = 𝑔 𝑚 𝑅 𝐶 1 𝐶 2 1 / 2 . ( 1 5 )

Equation (15) reveals that for high-pass and band-pass responses the pole frequency ( 𝜔 0 ) and quality factor ( 𝑄 0 ) can be adjusted by 𝑔 𝑚 , that is, by bias current of DDCCTA, without disturbing 𝜔 0 / 𝑄 0 . The 𝜔 0 and 𝑄 0 are orthogonally adjustable with simultaneous adjustment of 𝑔 𝑚 and 𝑅 such that the product 𝑔 𝑚 𝑅 remains constant and the quotient 𝑔 𝑚 / 𝑅 varies and vice versa. The resistance 𝑅 being a grounded one may easily be implemented as a variable resistance using only two MOS [17]. Equation (15) also indicates that high values of 𝑄 -factor will be obtained from moderate values of ratios of passive components, that is, from low component spread [22]. These ratios can be chosen as 𝑔 𝑚 𝑅 = ( 𝐶 1 / 𝐶 2 ) = 𝑄 0 . Hence, the spread of the component values becomes of the order of √ 𝑄 0 . This feature of the filter related to the component spread allows the realization of high 𝑄 0 values more accurately compared to the topologies where the spread of passive components becomes 𝑄 0 or 𝑄 2 0 . It can also be easily evaluated to show that the sensitivities of pole 𝜔 0 and pole 𝑄 0 are within unity in magnitude. Thus, the proposed structures, can be classified as insensitive.

A detailed study of the available similar type of single-active-element-based (such as CCCTA, DBTA, and DVCCCTA) voltage mode filters and the proposed one is given in Table 3. It reveals that the topology [18, 19] uses excessive number of passive components whereas the proposed topology uses one extra passive component, namely, resistor ( 𝑅 ) than [11, 15]. The proposed topology also provides the availability of a maximum number of simultaneous responses. Structures [11, 18, 19] use floating passive components and also use matching condition. Topology [11] needs input signal 𝑉 i n , − 𝑉 i n , and − 2 𝑉 i n ; hence there is requirement of additional circuits. Thus, it reveals that although the proposed topology realizes only LP, HP, and BP responses, it has two or more advantages over the other available topologies [11, 15, 18, 19].

tab3
Table 3: Comparative study of the available similar type of single-active-element-based VM filters.

To verify the functionality of the proposed single-DDCCTA-based voltage mode filter, SPICE simulations have been carried out using TSMC 0.25 μm CMOS process model parameters and supply voltages of 𝑉 D D = − 𝑉 S S = 1 . 2 5 V and 𝑉 B B = − 0 . 8 V . The filter is designed for a pole frequency of 𝑓 0 = 1 . 5 9  MHz, 𝑄 = 1 , the component values are found to be 𝐶 1 = 𝐶 2 = 1 0 0  pF, 𝑅 = 1  kΩ, and bias current of DVCCTA equals 100 μA. Figure 7 shows the simulation results for high-pass ( 𝑉 o u t 1 ), band-pass ( 𝑉 o u t 2 ), and low-pass ( 𝑉 o u t 3 ) filter responses which are available simultaneously.

361384.fig.007
Figure 7: Simulated responses of the proposed voltage mode filter.
3.2. MISO Current Mode Universal Filter

A multiple-input single-output (MISO) universal current mode (CM) filter is proposed in this section which is obtained by grounding voltage input in Figure 6 and exciting it with current inputs as shown in Figure 8. It employs a single DDCCTA, two grounded capacitors, and a grounded resistor. Analysis of this circuit gives the output current as 𝐼 o u t 1 = − 𝑠 2 𝐶 1 𝐶 2 𝑅 𝐼 i n 1 − 𝑠 𝐶 2 + 𝑔 𝑚 𝐼 i n 2 + 𝑠 𝐶 1 𝐼 i n 3 , 𝐼 𝐷 ( 𝑠 ) o u t 2 = 𝐼 i n 1 − 𝐼 i n 2 𝑠 𝐶 2 𝑅 𝑔 𝑚 + 𝑔 𝑚 𝐼 i n 3 + 𝐷 ( 𝑠 ) 𝐼 i n 4 𝐷 , ( 𝑠 ) ( 1 6 ) where 𝐷 ( 𝑠 ) = 𝑠 2 𝐶 1 𝐶 2 𝑅 + 𝑠 𝐶 2 + 𝑔 𝑚 . ( 1 7 )

361384.fig.008
Figure 8: Current mode universal filter.

Table 4 shows the availability of each filter response and the corresponding selection of input currents 𝐼 i n 1 , 𝐼 i n 2 , 𝐼 i n 3 , and 𝐼 i n 4 . Thus, the proposed structure is a four-input-single-output current mode filter. It may be noted that there is no component matching constraint for obtaining any filter response. The filter parameters are the same as given in (15). The grounded resistance ( 𝑅 ) may easily be implemented as variable one using only two MOS [17] for full electronic control of filter parameters. The 𝜔 0 , 𝑄 0 , and 𝜔 0 / 𝑄 0 can be orthogonally adjusted for low-pass, high-pass, and band-pass responses the way discussed in Section 3.1.

tab4
Table 4: The 𝐼 i n 1 , 𝐼 i n 2 , 𝐼 i n 3 , and 𝐼 i n 4 values selection for each filter function response.

A detailed study of the available similar type of active-element-based (such as CCCCTA, CCCDTA, and CCCCTA) CM filters and the proposed one is given in Table 5. It reveals that although the proposed structure needs one extra resistor, the reported structures [11, 13, 20, 21] suffer from one or more features. In addition some active elements are required to sense current in [13, 21]. Thus, structures in [11, 13, 20, 21] will require some extra circuits to compensate the shortcomings in their features in comparison to the proposed one.

tab5
Table 5: Comparative study of the available similar type of single-active-element-based CM filters.

The proposed universal MISO current mode filter is validated through SPICE simulations. The circuit of Figure 8 for a pole frequency of 𝑓 0 = 1 . 5 9   MHz, 𝑄 = 1 has been designed with the component values of 𝐶 1 = 𝐶 2 = 1 0 0  pF, 𝑅 = 1  kΩ, and bias current of DDCCTA equal to 100 μA. Figure 9(a) shows the simulation results for band pass ( 𝐼 o u t 1 ) and low pass ( 𝐼 o u t 2 ) filter responses which are available simultaneously for 𝐼 i n = 𝐼 i n 3 , 𝐼 i n 1 = 𝐼 i n 2 = 𝐼 i n 4 = 0 . Figure 9(b) shows the simulation results for band pass ( 𝐼 o u t 2 ) and high-pass ( 𝐼 o u t 1 ) filter responses which are available simultaneously for 𝐼 i n = 𝐼 i n 1 , 𝐼 i n 2 = 𝐼 i n 3 = 𝐼 i n 4 = 0 . Notch and all pass responses are shown in Figures 9(c) and 9(d) with 𝐼 i n = 𝐼 i n 2 = 𝐼 i n 4 , 𝐼 i n 1 = 𝐼 i n 3 = 0 and 𝑅 = 1  kΩ and 2 kΩ, respectively.

fig9
Figure 9: Simulated responses of the proposed current mode universal filter: (a) low pass and band pass; (b) high pass and band pass; (c) notch; (d) all pass.
3.3. Oscillator

The current mode filter of Figure 8 may be used as oscillator when output 𝐼 o u t 2 is connected to 𝐼 i n 1 as shown in Figure 10. The analysis of the circuit of Figure 10 gives the following characteristic equation: 𝑠 2 𝐶 1 𝐶 2 𝑅 + 𝑠 𝐶 2 𝑅 𝑔 𝑚 − 1 + 𝑔 𝑚 = 0 . ( 1 8 ) The condition and frequency of oscillation may be computed as 𝑔 C O : 𝑚 = 1 𝑅 , 𝜔 F O : 0 = 𝑔 𝑚 𝑅 𝐶 1 𝐶 2 . ( 1 9 ) The oscillations are available at outputs 𝑉 o u t 1 and 𝑉 o u t 2 , and they are related as 𝑉 o u t 1 𝑔 = − 𝑚 𝑠 𝐶 2 𝑉 o u t 2 . ( 2 0 ) Thus, these voltages exhibit quadrature relationship. The current oscillations are also available at high output impedance at 𝐼 o u t .

361384.fig.0010
Figure 10: Proposed Oscillator.

To verify the proposed circuit, an oscillator was designed for 1.59 MHz with 𝐶 1 = 𝐶 2 = 1 0 0  pF, 𝑅 = 1  kΩ, and bias current of 100 μA. The simulated current and quadrature voltage waveforms are shown in Figure 11 for which the total harmonic distortion is 1.28%.

fig11
Figure 11: Outputs of the proposed oscillator: (a) quadrature output voltages at 𝑉 o u t 1 and 𝑉 o u t 2 ; (b) current oscillation at 𝐼 o u t .
3.4. Voltage Amplifier, Current Amplifier, and Grounded Inductor

The proposed DDCCTA may also be configured for voltage and current amplifiers and grounded inductor simulator as shown in Figures 12, 13, and 14, respectively. The transfer functions may be expressed as follows:

361384.fig.0012
Figure 12: Voltage amplifier.
361384.fig.0013
Figure 13: Current amplifier.
361384.fig.0014
Figure 14: Grounded inductor simulator.

(i) voltage amplifier: 𝑉 o u t 𝑉 i n = 1 𝑅 𝑔 𝑚 , ( 2 1 )

(ii) current amplifier: 𝐼 o u t 𝐼 i n = 𝑅 𝑔 𝑚 , ( 2 2 )

(iii) grounded inductor simulator: 𝑍 i n = 𝑉 i n 𝐼 i n = 𝑠 𝐶 𝑅 𝑔 𝑚 . ( 2 3 ) It may be noted that the gain of amplifiers and inductance can be adjusted by 𝑔 𝑚 , that is, by varying bias current of DDCCTA.

To verify the proposed amplifiers, the simulations have been carried out for 𝑅 = 0 . 5  kΩ (2 kΩ) for voltage (current) amplifier and bias current of 25 μA to 400 μA. The results are depicted in Figures 15 and 16. The inductor simulator is also validated through simulation with 𝑅 = 0 . 5  KΩ, 𝐶 = 1 0 0  pF, and bias current of 90 μA. Figure 17 shows the simulated and theoretical results and there is close agreement between the two.

361384.fig.0015
Figure 15: Voltage gain.
361384.fig.0016
Figure 16: Current gain.
361384.fig.0017
Figure 17: Frequency response of grounded inductor.

4. Conclusion

A new analog building block, namely, DDCCTA, is presented and some of its properties are discussed. It is found that the proposed DDCCTA is useful up to about 201 MHz. As applications of the proposed DDCCTA, VM multifunction filter, CM universal filter, quadrature oscillator, voltage and current amplifiers, and grounded inductor simulator topology are presented. The resistor being grounded may easily be implemented as a variable one using only two MOS [17]. The simulation results verify the theory.

References

  1. G. Ferri and N. C. Guerrini, Low-Voltage Low-Power CMOS Current Conveyors, Kluwer Academic, London, UK, 2003.
  2. R. L. Geiger and E. Sanchez-Sinencio, “Active filter design using operational transconductance amplifiers: a tutorial,” IEEE Circuits and Devices Magazine, vol. 1, no. 2, pp. 20–23, 1985. View at Scopus
  3. A. S. Sedra and K. C. Smith, “A second generation current conveyor its application,” IEEE Transactions on Circuit Theory, vol. 17, no. 1, pp. 132–134, 1970. View at Scopus
  4. A. Fabre, O. Saaid, F. Wiest, and C. Boucheron, “High frequency applications based on a new current controlled conveyor,” IEEE Transactions on Circuit and Systems I, vol. 43, pp. 82–91, 1996.
  5. I. A. Awad and A. M. Soliman, “Inverting second generation current conveyors: the missing building blocks, CMOS realizations and applications,” International Journal of Electronics, vol. 86, no. 4, pp. 413–432, 1999. View at Scopus
  6. H. O. Elwan and A. M. Soliman, “Novel CMOS differential voltage current conveyor and its applications,” IEE Proceedings—Circuits Devices Systems, vol. 144, pp. 195–200.
  7. W. Chiu, S. I. Liu, H. W. Tsao, and J. J. Chen, “CMOS differential difference current conveyor and their applications,” IEE Proceedings—Circuits Devices Systems, vol. 143, pp. 91–96, 1996.
  8. C. Toumazou and A. Payne, “Current feedback opamp: a blessing in disguise?” IEEE Circuits and Devices Magazine, vol. 10, pp. 43–47, 1994.
  9. R. Prokop and V. Musil, “CCTA-a new modern circuit block and its internal realization,” in Proceedings of the International Conference on Electronic Devices and Systems, (IMAPSCZ '05), pp. 89–93, Brno, Czech Republic, 2005.
  10. W. Jaikla, P. Silapan, C. Chanapromma, and M. Siripruchyanun, “Practical implementation of CCTA based on commercial CCII and OTA,” in Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, (ISPACS '08), pp. 1–4, Bangkok, Thailand, February 2009. View at Publisher · View at Google Scholar
  11. M. Siripruchyanun and W. Jaikla, “Current controlled current conveyor transconductance amplifier (CCCCTA): a building block for analog signal processing,” Electrical Engineering, vol. 90, no. 6, pp. 443–453, 2008. View at Publisher · View at Google Scholar
  12. D. Biolek, “CDTA—building block for current-mode analog signal processing,” in Proceedings of the European Conference on Circuit Theory and Design, (ECCTD '03), pp. 397–400, Krak ów, Poland, September 2003.
  13. M. Siripruchyanun and W. Jaikla, “CMOS current-controlled current differencing transconductance amplifier and applications to analog signal processing,” International Journal of Electronics and Communications, vol. 62, no. 4, pp. 277–287, 2008. View at Publisher · View at Google Scholar · View at Scopus
  14. A. Jantakun, N. Pisutthipong, and M. Siripruchyanun, “A synthesis of temperature insensitive/electronically controllable floating simulators based on DV-CCTAs,” in Proceedings of the 6th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, (ECTI-CON '09), pp. 560–563, Pattaya, Chonburi, Thailand, May 2009. View at Publisher · View at Google Scholar
  15. W. Jaikla, M. Siripruchyanun, and A. Lahiri, “Resistorless dual-mode quadrature sinusoidal oscillator using a single active building block,” Microelectronics Journal, vol. 42, no. 1, pp. 135–140, 2010. View at Publisher · View at Google Scholar · View at Scopus
  16. H. P. Chen, “Versatile universal voltage-mode filter employing DDCCs,” International Journal of Electronics and Communications, vol. 63, no. 1, pp. 78–82, 2009. View at Publisher · View at Google Scholar · View at Scopus
  17. H. P. Chen, “High-input impedance voltage-mode multifunction filter with four grounded components and only two plus-type DDCCs,” Active and Passive Electronic Components, vol. 2010, Article ID 362516, 5 pages, 2010. View at Publisher · View at Google Scholar
  18. N. Herencsar, K. Vrba, J. Koton, and I. Lattenberg, “The conception of differential-input buffered and transconductance amplifier (DBTA) and its application,” IEICE Electronics Express, vol. 6, no. 6, pp. 329–334, 2009. View at Publisher · View at Google Scholar
  19. N. Herencsár, J. Koton, K. Vrba, and I. Lattenberg, “New voltage-mode universal filter and sinusoidal oscillator using only single DBTA,” International Journal of Electronics, vol. 97, no. 4, pp. 365–379, 2010. View at Publisher · View at Google Scholar
  20. M. Siripruchyanun and W. Jaikla, “Electronically controllable current-mode universal biquad filter using single DO-CCCDTA,” Circuits, Systems, and Signal Processing, vol. 27, no. 1, pp. 113–122, 2008. View at Publisher · View at Google Scholar
  21. S. Mangkalakeeree, D. Duangmalai, and M. Siripruchyanun, “Current-mode KHN filter using single CCCCTA,” in Proceedings of the 7th PSU Engineering Conference, pp. 306–309, Hat-Yai, Thailand, May 2009.
  22. S. I. Liu, “High input impedance filters with low component spread using current-feedback amplifiers,” Electronics Letters, vol. 31, no. 13, pp. 1042–1043, 1995. View at Publisher · View at Google Scholar