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Journal of Electrical and Computer Engineering
Volume 2011 (2011), Article ID 701730, 7 pages
A Wide Lock-Range Referenceless CDR with Automatic Frequency Acquisition
Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), San 31, Hyojadong, Pohang 790-784, Republic of Korea
Received 26 April 2011; Accepted 16 June 2011
Academic Editor: Woogeun Rhee
Copyright © 2011 Seon-Kyoo Lee et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
- B. Razavi, “Design of high-speed circuits for optical communication systems,” in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 315–322, San Diego, Calif, USA, May 2001.
- J. C. Scheytt, G. Hanke, and U. Langmann, “A 0.155, 0.622 and 2.488-Gb/s automatic bit-rate selecting clock and data recovery IC for bit-rate transparent SDH systems,” IEEE Journal of Solid-State Circuits, vol. 34, no. 12, pp. 1935–1943, 1999.
- D. Belot, L. Dugoujon, and S. Dedieu, “A 3.3-V power adaptive 1244/622/155 Mbit/s transceiver for ATM, SONET/SDH,” IEEE Journal of Solid-State Circuits, vol. 33, no. 7, pp. 1047–1058, 1998.
- M. H. Perrott, Y. Huang, R. T. Baird et al., “A 2.5-Gb/s multi-rate 0.25-μm CMOS clock and data recovery circuit utilizing a hybrid analog/digital loop filter and all-digital referenceless frequency acquisition,” IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2930–2942, 2006.
- H. Nosaka, E. Sano, K. Ishii et al., “A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector,” IEEE Journal of Solid-State Circuits, vol. 39, no. 8, pp. 1361–1365, 2004.
- J. P. Frambach, R. Heijna, and R. Krösschell, “Single reference continuous rate clock and data recovery from 30Mbit/s to 3.2Gbit/s,” in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 375–378, Scottsdale, Ariz, USA, May 2002.
- R.-J. Yang, et al., “A 200-Mbps~2-Gbps continuous-rate clock-and-data-recovery circuit,” IEEE Transactions on Circuits and Systems I, vol. 53, no. 4, pp. 842–847, 2006.
- R.-J. Yang, K. H. Chao, S. C. Hwu, C. K. Liang, and S. I. Liu, “A 155.52 Mbps-3.125 gbps continuous-rate clock and data recovery circuit,” IEEE Journal of Solid-State Circuits, vol. 41, no. 6, Article ID 1637602, pp. 1380–1390, 2006.
- D. Dalton, K. Chai, E. Evans et al., “A 12.5-Mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2713–2724, 2005.
- M. S. Hwang, S. Y. Lee, J. K. Kim, S. Kim, and D. K. Jeong, “A 180-Mb/s to 3.2-Gb/s, continuous-rate, fast-locking CDR without using external reference clock,” in Proceedings of the IEEE Asian Solid-State Circuits Conference, pp. 144–147, Jeju, korea, November 2007.
- A. X. Widmer and P. A. Franaszek, “A DC-balanced, partitioned-block, 8B/10B transmission code,” IBM Journal of Research and Development, vol. 27, no. 5, pp. 440–451, 1983.
- S.-K. Lee, Y. S. Kim, H. Ha, Y. Seo, H. J. Park, and J. Y. Sim, “A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate,” in Proceedings of the IEEE International Solid-State Circuits Conference ISSCC 2009, vol. 52, pp. 184–185, San Francisco, Calif, USA, February 2009.
- J. D. H. Alexander, “Clock recovery from random binary signals,” Electronics Letters, vol. 11, no. 22, pp. 541–542, 1975.