480 MHz 10-tap Clock Generator Using Edge-Combiner DLL for USB 2.0 Applications

<table>Block diagrams of candidate clock generator based on DLLs. Upper block diagram is the structure that consists of one ECDLL and one DLL. The ECDLL has a multiplication ratio of 40. Bottom block diagram is the structure that consists of three ECDLL and one DLL. The DLL1, DLL2, and DLL3 have multiplication ration of two, four, and five, respectively.</table>

Journal of Electrical and Computer Engineering

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Figure 3

Figure 3: 480 MHz 10-tap Clock Generator Using Edge-Combiner DLL for USB 2.0 Applications 