- About this Journal ·
- Abstracting and Indexing ·
- Aims and Scope ·
- Article Processing Charges ·
- Author Guidelines ·
- Bibliographic Information ·
- Citations to this Journal ·
- Contact Information ·
- Editorial Board ·
- Editorial Workflow ·
- Free eTOC Alerts ·
- Publication Ethics ·
- Recently Accepted Articles ·
- Reviewers Acknowledgment ·
- Submit a Manuscript ·
- Subscription Information ·
- Table of Contents
Journal of Electrical and Computer Engineering
Volume 2012 (2012), Article ID 365091, 12 pages
Memory Map: A Multiprocessor Cache Simulator
1Department of Computer Science & Engineering, Chitkara University, Baddi, Solan 174103, India
2Department of Computer Science & Engineering and Information Technology, Jaypee University of Information Technology, Waknaghat, Solan 173234, India
Received 7 February 2012; Accepted 31 May 2012
Academic Editor: Vivek Kumar Sehgal
Copyright © 2012 Shaily Mittal and Nitin. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
- J. L. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann, 4th edition, 2006.
- M. B. Kamble and K. Ghose, “Analytical energy dissipation models for low power caches,” in Proceedings of the International Symposium on Low Power Electronics and Design, pp. 143–148, August 1997.
- J. Reineke, D. Grund, C. Berg, and R. Wilhelm, “Predictability of cache replacement policies,” AVACS Technical Report no. 9, SFB/TR 14 AVACS, ISSN:18609821, 2006.
- R. Banakar, S. Steinke, B. S. Lee, M. Balakrishnan, and P. Marwedel, “Scratchpad memory: a design alternative for cache on-chip memory in embedded systems,” in Proceedings of the 10th International Symposium on Hardware/Software Codesign (CODES '02), pp. 73–78, May 2002.
- P. R. Panda, N. D. Dutt, and A. Nicolau, “Efficient utilization of scratch-pad memory in embedded processor applications,” in Proceedings of the European Design & Test Conference, pp. 7–11, March 1997.
- S. Pasricha, N. D. Dutt, and M. Ben-Romdhane, “BMSYN: bus matrix communication architecture synthesis for MPSoC,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 8, pp. 1454–1464, 2007.
- I. Issenin, E. Brockmeyer, B. Durinck, and N. D. Dutt, “Data-reuse-driven energy-aware cosynthesis of scratch pad memory and hierarchical bus-based communication architecture for multiprocessor streaming applications,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 8, pp. 1439–1452, 2008.
- D. Cho, S. Pasricha, I. Issenin, N. D. Dutt, M. Ahn, and Y. Paek, “Adaptive scratch pad memory management for dynamic behavior of multimedia applications,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 4, pp. 554–567, 2009.
- Nomadik platform, http://www.st.com/.
- PC205 platform, http://www.picochip.com/.
- Philips nexperia platform, http://www.semiconductors.philips.com/.
- STMicroelectronics, http://www.st.com/internet/mcu/home/home.jsp.
- OMAP5910 platform, http://www.ti.com/.
- J. Chung, H. Chafi, C. C. Minh et al., “The common case transactional behavior of multithreaded programs,” in Proceedings of the 12th International Symposium on High-Performance Computer Architecture, pp. 266–277, February 2006.
- I. Issenin, E. Brockmeyer, B. Durinck, and N. Dutt, “Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies,” in Proceedings of the 43rd annual Design Automation Conference (DAC '06), pp. 49–52, 2006.
- B. Ackland, A. Anesko, D. Brinthaupt et al., “Single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP,” IEEE Journal of Solid-State Circuits, vol. 35, no. 3, pp. 412–424, 2000.
- Intel Pentium 4 and Intel Xeon Processor Optimization Reference Manual, http://www.cs.washington.edu/education/courses/csep501/05au/x86/24896607.pdf.
- S. Roy, “H-NMRU: a low area, high performance cache replacement policy for embedded processors,” in Proceedings of the 22nd International Conference on VLSI Design, pp. 553–558, January 2009.
- M. A. Vega Rodríguez, J. M. Sánchez Pérez, and J. A. Gómez Pulido, “An educational tool for testing caches on symmetric multiprocessors,” Microprocessors and Microsystems, vol. 25, no. 4, pp. 187–194, 2001.
- W. C. Jeun and S. Ha, “Effective OpenMP implementation and translation for Multiprocessor System-On-Chip without using OS,” in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC '07), pp. 44–49, January 2007.
- T. D. C. Burger and T. M. Austin, “The SimpleScalar Tool Set, Version 2.0,” Tech. Rep. CS-TR-1997-1342, University of Wisconsin, Madison, Wis, USA, 1997.
- Jason Loew, http://www.cs.binghamton.edu/~msim/.
- T. Rissa, A. Donlin, and W. Luk, “Evaluation of systemC modelling of reconfigurable embedded systems,” in Proceedings of the Design, Automation and Test in Europe (DATE '05), pp. 253–258, March 2005.
- Open SystemC Iniative OSCI, SystemC documentation, 2004, http://www.systemc.org/.
- C. L. Chen and C. K. Liao, “Analysis of vector access performance on skewed interleaved memory,” in Proceedings of the 16th Annual International Symposium on Computer Architecture, pp. 387–394, June 1989.
- K. Hwang and F. A. Briggs, Computer Architecture and Parallel Processing, McGraw-Hill, 1984.
- D. A. Patterson and J. L. Hennesy, Computer Organization and Design: The Hardware/Software Interface, Morgan Kauffmann, 1994.
- M. Farrens and A. Park, “Dynamic base register caching: a technique for reducing address bus width,” in Proceedings of the 18th International Symposium on Computer Architecture, pp. 128–137, May 1991.
- A. Samih, Y. Solihin, and A. Krishna, “Evaluating placement policies for managing capacity sharing in CMP architectures with private caches,” ACM Transactions on Architecture and Code optimization, vol. 8, no. 3, 2011.