Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="484962.fig.0010a" src="https://static.hindawi.com/articles/jece/volume-2012/484962/figures/484962.fig.0010a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Speedup for the serial decoder at QCIF resolution</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="484962.fig.0010b" src="https://static.hindawi.com/articles/jece/volume-2012/484962/figures/484962.fig.0010b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Speedup for the parallel decoder at QCIF resolution</td></tr></table></td></tr></table>

<table>Speedup of the MPEG-4 SP decoder running on an X86 quad-core (in black) and on a PowerPC e500 8-core (in gray) processors.</table>

Journal of Electrical and Computer Engineering

fig10

Figure 10

Figure 10: Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs 