Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="484962.fig.0011a" src="https://static.hindawi.com/articles/jece/volume-2012/484962/figures/484962.fig.0011a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Speedup for the serial decoder according to the resolution</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="484962.fig.0011b" src="https://static.hindawi.com/articles/jece/volume-2012/484962/figures/484962.fig.0011b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Speedup for the parallel decoder according to the resolution</td></tr></table></td></tr></table>

<table>Speedup of the MPEG-4 SP decoder on an Intel i7-870 processor at QCIF (red), SD (blue) and HD (green) resolutions.</table>

Journal of Electrical and Computer Engineering

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Figure 11

Figure 11: Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs 