A State-Based Modeling Approach for Efficient Performance Evaluation of Embedded System Architectures at Transaction Level

Table 2

Behavior of Stage3 activity described by using the state-based modeling approach.

Current state	Next state		Actions
	Condition	State	Condition	Action
𝑠0	InputStage3	𝑠1	—	CcStage3=0
𝑠1	𝑡=𝑇Proc	𝑠2	—	CcStage3=Cc𝑠1
𝑠2	𝑡=𝑇Idle AND 𝑘<4	𝑠1	—	CcStage3=0
	𝑡=𝑇Idle AND 𝑘=4	𝑠0		OutputSymbol