Research Article
A State-Based Modeling Approach for Efficient Performance Evaluation of Embedded System Architectures at Transaction Level
Table 5
Maximal computational complexity and utilization of the processing resources observed for the two architectures considered.
| | Architecture I | Architecture II | | | | | | Maximal computational complexity (GOPS) | Resource usage (%) | Maximal computational complexity (GOPS) | Resource usage (%) | Maximal computational complexity (GOPS) | Resource usage (%) |
| | OFDMDemodulator | 1,612 | 20 | — | — | 0,322 | 100 | | ChannelEstimator | 0,406 | 48 | — | — | 0,244 | 80 | | Equalizer | 0,151 | 12 | — | — | 0,03 | 80 | | TurboDecoder | — | — | 221,77 | 8 | 177,49 | 10 | | Application | 1,612 | 80 | 221,77 | 8 | 177,812 | — |
|
|
