VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

Table 1

Complexity and decoding delay of log-MAP decoders.

Operating mode	Mem. requirement [bits]	Number of DFUs	Decoding delay steps
Continuous	(𝑃+1)2^𝐺𝑤𝐿	1	3P/2P
Terminated	[(𝑃−3)2^𝐺+2^𝑏+1+2]𝑤𝐿	1	3P/2P
Truncated	[(𝑃−1)2^𝐺+2^𝑏+1]𝑤𝐿	1	3P/2P