A New Efficient and Reliable Dynamically Reconfigurable Network-on-Chip

Table 2

RKT-switch synthesis results.

Data bus width (bits)	Virtex V			Virtex VI			Virtex VII
	Slices Registers	Slices LUTs	𝑓 [MHz]	Slices Registers	Slices LUTs	𝑓 [MHz]	Slices Registers	Slices LUTs	𝑓 [MHz]
24	3503	4146	303.93	3537	5675	429.54	3540	5571	459.71
32	4308	4998	311.85	4377	6661	431.04	4340	6542	459.68
64	8402	8743	306.28	8360	11672	419.21	8362	11681	441.62