FPGA Implementation of Gaussian Mixture Model Algorithm for 47 fps Segmentation of 1080p Video

Table 1

Performances of the circuit of Figure 2 implemented on different FPGA and comparison with previous art.

Target FPGA	Circuit	LUT/ALUT	Flip Flop	Slice/LAB	DSP/MULT	Frequency (MHz)	HD fps
Virtex6 (xc6vlx75t)	proposed circuit	922/46560	0/93120	265/11640	0/288	97.19	46
Virtex5 (xc5vlx50)	proposed circuit	844/28800	0/28800	301/7200	0/48	91.03	43
	Reference [22]	705/28800	0/28800	313/7200	10/48	51.30	24
StratixIV (SGX230HF35C2)	proposed circuit	1150/182400	0/182400	81/9120	0/1288	98.12	47
Spartan3 (xc3s1000)	proposed circuit	1797/15360	0/15360	1010/7680	0/24	35.30	17