Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration

<table>Phasor diagram of AM and PM components in magnetically coupled VCOs.</table>

Journal of Electrical and Computer Engineering

Figure 4: Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration 