Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration

<table>Measured tuning curves of dual LC VCOs across PVT corners.</table>

Journal of Electrical and Computer Engineering

Figure 9: Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration 