Journal of Electrical and Computer Engineering

Research Article

Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs

Figure 14

(a) Symmetric SG/LP configuration TG topology of FinFET XOR, (b) asymmetric SG/LP configuration TG topology of FinFET XOR.
454392.fig.0014a
(a)
454392.fig.0014b
(b)