Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs

Table 10

Comparison of full adder circuits.

Topology	𝐼OFF (pA)	𝑡P (ps)	Static power * delay (zJ)	Number of transistors	Dynamic energy (aJ)
Mirror	49.85	37.05	2.21	24	1206
14T	38.47	24.03	1.10	14	242
TG	74.79	26.56	2.38	26	1191
PTL	196.35	22.5	5.3	20	500