Research Article
Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs
Table 5
Results for the carry circuit.
| IG/LP mode | Symmetric = −0.2 V | [4] Symmetric = −0.2 V | Asymmetric = 0 V |
| (pA) | 16.42 | 22.10 | 2.81 | (ps) | 11.94 | 23.88 | 13.63 | Static power * delay (yJ) | 235.26 | 633.30 | 45.96 |
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