Research Article
Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs
Table 6
Results for the complete mirror full adder.
| IG/LP mode | Symmetric = −0.2 V | Asymmetric = 0 V |
| (pA) | 49.85 | 6.24 | (ps) | 37.05 | 39.52 | Static power * delay (zJ) | 2.21 | 0.30 |
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