- About this Journal ·
- Abstracting and Indexing ·
- Advance Access ·
- Aims and Scope ·
- Article Processing Charges ·
- Articles in Press ·
- Author Guidelines ·
- Bibliographic Information ·
- Citations to this Journal ·
- Contact Information ·
- Editorial Board ·
- Editorial Workflow ·
- Free eTOC Alerts ·
- Publication Ethics ·
- Reviewers Acknowledgment ·
- Submit a Manuscript ·
- Subscription Information ·
- Table of Contents

Journal of Electrical and Computer Engineering

Volume 2013 (2013), Article ID 568780, 16 pages

http://dx.doi.org/10.1155/2013/568780

## Message Broadcasting via a New Fault Tolerant Irregular Advance Omega Network in Faulty and Nonfaulty Network Environments

Department of Computer Science & Engineering and Information & Communication Technology, Jaypee University of Information Technology, Waknaghat, Solan 173234, India

Received 22 January 2013; Revised 11 March 2013; Accepted 28 March 2013

Academic Editor: Bin-Da Liu

Copyright © 2013 Ved Prakash Bhardwaj and Nitin. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

Interconnection Network (IN) is a key element for all parallel processing applications. Multistage Interconnection Network (MIN) is an efficient IN for these applications, as it has the quality of excellent performance at low cost with high reliability. MINs are effective medium for message broadcasting. Doing the same task in faulty situations is a critical challenge. In this paper, we have presented a new Fault Tolerant Interconnection Network named as Irregular Advance Omega Network (IAON); also we have presented its routing algorithm. IAON is the modified form of Advance Omega Network. The proposed MIN can endure multiple faults and provides a suitable path between every source to every destination. We have examined the fault tolerance capacity of IAON and compared its performance with other existing MINs. In order to check the performance of proposed MIN, message broadcasting was performed in three conditions as follows: (1) when network was fault free; (2) when network was Single Switch Faulty in every stage; (3) when network was Double Switch Faulty in every stage. Results showed that IAON performed better than the earlier proposed MINs.

#### 1. Introduction and Motivation

Interconnection Networks have a broad range of application specific domains, for example, On Chip Networks, Storage Area Networks, Local Area Networks, and Wide Area Networks. In all these networks, the basic component is IN which connects various modules with each other [1–5] and therefore, these modules have the proficiency of communication [6–12]. These modules can be of any type like memory, I/O component, processor, functional units, register files, and so forth. MINs are essential INs for various parallel computing and telecommunication applications such as Omega Network, Advance Omega Network, and Clos Network. It is better than the crossbar INs in terms of cost and performance. Generally, a MIN consists of input and output devices which are connected via a number of switching stages [13–21]. Based on the availability of paths, MIN may be blocking or nonblocking. Blocking MINs have a unique path between each input and output device, for example, Omega Network. In nonblocking MIN, any input device can be connected to any output device without affecting the existing connection pattern, for example, Clos Network. Nonblocking characteristic shows multipath nature of MINs. Due to the multipath nature of MINs, the concept of fault tolerance came into the limelight [22–34]. Currently, fault tolerance is one of the most widely researched topics [26–34] in the field of MINs. It is defined as

“The basic idea for fault-tolerance is to provide multiple paths between source and destination so that alternate paths can be used in case of faults [16].”

Moreover, data packets can be transmitted using message unicasting method, message multicasting method, and message broadcasting method. In unicasting, a data packet is sent from a source to a single destination. In case of multicasting, a data packet is sent from a source to an arbitrary number of destinations, while in the broadcasting, a data packet is transmitted from a source to all given destinations. In this research work, we have applied message broadcasting technique to analyze the performance of proposed MIN. Adaptive dynamic rerouting strategy [30] was applied on MALN [15], IASEN-2 [18], and IAON for data transmission. In case of faulty switching elements (SEs), data packets were dynamically rerouted [30] from faulty SE to nonfaulty SE to get the desired destination.

##### 1.1. Issue of Fault Tolerance in Multistage Interconnection Networks

The concept of fault tolerance in MINs has been demonstrated in Figure 1. In this figure, we have considered a sample IN which has 2 stages. SEs of this network are , , , , , and . In Figure 1, the primary, first alternate, and second alternate paths are shown by green, light blue, and purple arrows, respectively. Initially, it is assumed that the network is nonfaulty and data will go through a primary path from a source to a destination or to multiple destinations. After this, it is assumed that one SE is faulty in each stage; therefore, data will be routed through first alternate path. These types of networks are known as Single Switch Fault Tolerant Network. Finally, it is assumed that two SEs are faulty in each stage therefore, data will choose second alternate path. These types of networks are known as Double Switch Fault Tolerant Network. If more than two SEs are faulty in each stage then data packets will not reach to their given destinations.

Various researchers have concentrated on fault tolerance [26–34] issue in order to increase the reliability of MINs. Literature survey revealed that in [13–34] ample work has been carried out on Single Switch Fault Tolerant Networks. However, providing an efficient communication through Double Switch Fault Tolerant Network still remained a major research challenge. Towards this problem, we have developed a Double Switch Fault Tolerant MIN named as Irregular Advance Omega Network. It is a reliable IN which provides an excellent communication between every pair of source and destination in presence of multiple faults and also produces better results than the earlier proposed MINs. Furthermore, it is compared with Modified Alpha Network (MALN) [15] and IASEN-2 [18]. Both MALN [15] and IASEN-2 [18] are 4-stage INs for network size and can tolerate single switch fault in each stage simultaneously.

The rest of the paper is organized as follows. In Section 2, previous fault tolerant networks have been discussed. Section 3 explains the structure of IAON. In Section 4 routing algorithm has been explained. In Section 5, performances of MALN, IASEN-2, and IAON were analyzed with simulation results. Finally, conclusion is presented in Section 6 followed by references.

Before moving to next section, let us have a look on the symbols which are used throughout the paper. Table 1 shows these symbols and their meanings.

#### 2. Preliminaries and Background

Before reaching on next section, we have given a succinct description of MALN [15] and IASEN-2 [18] which were compared with IAON.

##### 2.1. Modified Alpha Network

MALN has sources and destinations with stages. It is divided into two subgroups with sources and destinations in each. The sources and destinations are connected with the entire network through multiplexer and demultiplexers, respectively. The SEs of , , and stages are connected through auxiliary links [15]. In the routing process, MALN takes the source and destination addresses in binary format. In the first step, it checks the MSB of the destination address and selects one subnetwork [15], that is, G0 or G1. If the address of SE is known then data will be sent through the shortest path and further routing is not required. If the SE is busy then it routes the data through the auxiliary link otherwise, it drops the request and follows the next step [15]. In the next step, the secondary path is selected and we have to set the MSB of routing tag as 1. In this case, data will be moved through the intermediate stages and if the SE is busy in any of the stages except the last one then the whole procedure is repeated again [15]. In the further step, it routes the data to auxiliary switch of the same stage and then send data to its destination address [15].

##### 2.2. Irregular Augmented Shuffle Exchange Network-2

IASEN-2 has stages with source and destinations. In this network, first and last stages contain SEs. In the same way, second and third stages have SEs. The SEs of all the stages are allied through the connecting links [18]. In second and third stage it has some extra interconnecting links which are known as auxiliary links [18]. The sources and destinations have a strong connectivity with the entire network through multiplexer and demultiplexers. As far as the routing process of IASEN-2 is concerned, if a SE receives a request from a source or from the SE of previous stage it immediately forwards it towards the SE of next stage [18]. In case if this particular SE is faulty or busy then request will arrive on the alternate SE of the same stage. If the alternate SE is also busy or faulty then network will be failed to send the request to its appropriate destination. If it does not happen so, then it sends the request towards the destination side [18]. If request arrives at the SE of last stage then it will be sent to its appropriate destination through demultiplexer.

#### 3. Proposed Interconnection Network

The structure of Irregular Advance Omega Network is based on Advance Omega Network [14]. IAON has 3 stages for every network size. In this network, sources, multiplexers, demultiplexers, and destinations are represented by , Mux, Demux, and , respectively. The sizes of Mux and Demux are and , respectively. Presently, there are 16 Mux and 16 Demux in this network. Each Mux connects the sources to SEs of first stage and each Demux connects SEs of third stage to destinations. In first and third stage, the network has 4 SEs in each, while second stage has 3 SEs.

The size of SEs in first and third stage is (/4 × 4) and (4 × /4), respectively. In the second stage, SE and have the size 5 × 5. The size of SE is 6 × 6. Each source is connected with two other SEs of first stage through auxiliary links. In the same way, each destination is connected with two other SEs of third stage through auxiliary links. In Figure 2, auxiliary links of second stage are shown by green colour. In IAON, each source and each destination have one primary and two alternate SEs. If the SE is directly connected with any source or any destination then it will be primary SE of that particular source or destination. If it is indirectly (through auxiliary links) connected with any source or destination, then it will be first or second alternate SE of that particular source or destination. Hence, SEs *a*,* b*, and are the primary, first, and second alternate SEs for source 0, respectively. Equally, we can see the primary, first alternate, and second alternate SEs of other sources and destinations in Figure 2.

Redundancy graph [15] of IAON is shown in Figure 3. In this figure, source and destination are shown by green nodes.

All the SEs are shown by black nodes, while auxiliary links are shown by green lines. This graph represents that the proposed MIN has the potency of good communication in faulty cases.

#### 4. Routing Algorithm of IAON

Algorithm_IAON_Broadcast is designed for message broadcasting purpose (Algorithm 1). Initially, we have to take the total number of destinations as input from user side then as mentioned in the algorithm function FIRST-STAGE *(Source)* will be called. This function will check the nonfaulty SE in the first stage and transmit the data packets towards that particular SE. If all the SEs that is, primary, first alternate, and second alternate SE are busy or faulty then network will be failed and data transmission process will be stopped. In function SECOND-STAGE *(Source)*, initially primary SE will collect the data packets from the nonfaulty SE of first stage. If SE is faulty or busy then these data packets will be dynamically rerouted through first alternate SE . In case, if SE is also faulty then second alternate SE will receive all the data packets.

If all the SEs of second stage are busy or faulty then path will be blocked and data transmission will not be possible in this case. In function THIRD-STAGE *(Source)*, the primary SE obtains the data packets from nonfaulty SE of second stage. This function will also search the nonfaulty SE in third stage and send the data packets to nonfaulty SE. Further, data packets will be transmitted to all destinations. If it does not happen so, IAON will be failed and data transmission process will be stopped.

##### 4.1. Explanation of Routing Algorithm

In this section, we have demonstrated the routes of data packets in Nonfaulty, Single Switch Faulty and Double Switch Faulty cases for source 5.

*Case 1 (route of data packets when network is nonfaulty). *In this case, we have assumed that IAON does not have any fault and data packets are easily transmitted through the primary SEs. Figure 4 shows the route of data packets through primary SEs. In this case the primary paths for source 5 are as follows: *Path 1*: *Path 2*: *Path 3*: *Path 4*: .

It shows that SEs , , , , , and will be the primary SEs for source 5, and these are shown by green colour in Figure 4.

*Case 2 (route of data packets when network is Single Switch Faulty in every stage). *In this case, we have assumed that SEs *b*, *e*, and are faulty then first alternate paths for source 5 are as follows: *Path 1*: *Path 2*: *Path 3*: .

Figure 5 shows that SE is connected with SE through Mux; hence, SE is the first alternate SE of first stage for source 5. Similarly, SE of second stage will be the first alternate SE of second stage. At last in the third stage, Figure 5 shows that SE is allied with SEs and . Therefore, the SEs and will be the first alternate SEs of second stage and these SEs are shown by light blue colour in Figure 5. However, SE is not connected with SE ; hence, it will be treated as primary SE and it is shown by green colour in Figure 5.

*Case 3 (route of data packets when network is Double Switch Faulty in every stage). *In this case, we have assumed that SEs , , , , , and are faulty then second alternate paths for source 5 are as follows: *Path 1*: *Path 2*: .

Figure 6 shows that SE is connected with SE through Mux. Hence, SE is the second alternate SE of first stage for source 5. Similarly, SE of second stage will be the second alternate SE of second stage. At last in the third stage, Figure 6 shows that SE and are allied with SEs and . Therefore, the SEs and will be the second alternate SEs of second stage, and all these SEs are shown by purple colour in Figure 6.

All the discussed cases clearly explained the proposed routing algorithm. This description also proved that IAON is a Double Switch Fault Tolerant MIN.

##### 4.2. Theorem

Minimum number of alternate paths between every source to every destination is 21.

*Proof. *In Section 3, it is given that the second stage of IAON connects the SEs of first stage to the SEs of third stage. It shows that the second stage is an important stage of IAON and all the alternate paths are generated by this stage. It is given in Figure 2. This figure shows that if a SE of first stage sends the data packets to the SE of second stage then it will be received by any one SE of second stage. In this way, SEs *e*, *f*, and will generate the 3 different paths. Remaining 4 paths will be generated by auxiliary links of second stage. In this way, we will have the total 7 paths, which are generated by the second stage of IAON. These paths are as follows: *Path 1*: *Path 2*: *Path 3*: *Path 4*: *Path 5*: *Path 6*: *Path 7*: .

Further, it is known that each source is allied with 3 SEs of first stage. Therefore, total number of alternate paths will be .

The above discussed hypothesis clearly proves our theorem and tells us that the given theorem is applicable on each network size of IAON. Furthermore, we have taken an example to understand the same fact.

*Example 1. *Let the source be 9 and let destination are 2. Figure 2 shows that source 9 is connected with SEs *c*, *a*, and . Equally, destination 2 is connected with SEs , , and . To obtain the alternate paths again we have considered three different cases.

*Case 1 (when data packets will be transmitted through primary of first stage). *In this case the alternate paths are as follows: *Path 1*: *Path 2*: *Path 3*: * **Path 4*: *Path 5*: *Path 6*: *Path 7*: .

*Case 2 (when data packets will be transmitted through first alternate SE of first stage). *In this case the alternate paths are as follows:

*Path 1*: *Path 2*: *Path 3*: *Path 4*: *Path 5*: *Path 6*: *Path 7*: .

*Case 3 (when data packets will be transmitted through second alternate SE of first stage). *In this case the alternate paths are as follows: *Path 1*: *Path 2*: *Path 3*: *Path 4*: *Path 5*: *Path 6*: *Path 7*: .

In all these cases the total numbers of paths are 21. It proved that IAON has minimum 21 alternate paths from any source to any destination.

#### 5. Performance Analysis and Simulation Results

To evaluate the performance of IAON, we have simulated the proposed routing algorithm in java technology using JDK 1.6 platform. We have compared the probability of acceptance, throughput, processor utilization and processing power of IAON with MALN [15] and IASEN-2 [18]. Basically, message broadcasting was performed in our simulation. In nonfaulty case, data packets will take the shortest path from source node to destination node and we assumed that the data transmission time between two nodes is 0.1 ms. In faulty situation, we have dynamically rerouted the data packets from faulty to appropriate nonfaulty node. Therefore, these data packets can be transmitted to the given destinations. In faulty cases, we have assumed that a data packet takes 0.2 ms in its rerouting process. Routing time of a data packet is explained in Sections 5.3 to 5.7. Before coming on the simulation results let us have a look on the various performance parameters.

##### 5.1. Request Generation Probability ()

The term “Request Generation Probability” represents the number of data packets generated on a source node and these generated data packets can be transmitted to destinations through IAON, MALN [15], and IASEN-2 [18]. In this simulation, is assumed to be . Data packets were generated and transmitted to MALN, IASEN-2, and IAON in faulty and nonfaulty cases.

##### 5.2. Bandwidth (BW)

To calculate the BW of IAON, MALN, and IASEN-2, we have applied the probabilistic method on these networks. Before calculating the BW of IAON, MALN, and IAEN-2, let us have a look on the probabilistic method [13–17].

Assume that a switching element has input lines and output lines as shown in Figure 7 and therefore, the size of SE is .

As we know that is the Request Generation Probability and when it is applied on the input lines of SE then it collects the data packets and transmits them towards the SE of next stage. Hence,

“Probability [13, 14] of not getting the request from “a” inputs is: ”,

“Probability [13, 14] of one output getting the request from “a” inputs is: ”,

“Probability [13, 14] of one output getting the request from “a” inputs is: ”,

“Total number of requests [13, 14] that are passed per unit time is: ”.

m, “Total number of requests that are passed per unit time is: ”.

The output of a stage will be the input of next stage and finally the output rate of last stage will be the BW of a MIN [13–17]. In this way, BW of a MIN can be obtained easily. The definition of BW is as follows.

*Definition 2. **“BW is defined as the mean number of active memory modules in a transfer cycle of INs and therefore, BW is the total number of request matured [14–17].”*

According to Definition 2, BW of a MIN will be bytes/ms or bytes/ms and .

Here, is the total number of destinations () and is also the request generation probability.

###### 5.2.1. BW Calculations of MALN, IASEN-2, and IAON

To calculate the BW we have assumed that total number of stages for each network size will be constant that is, for MALN, IASEN-2, and IAON it will be 4, 4, and 3, respectively.

Probability equations for MALN [15] are as follows: As we know, is the total number of destinations.

Probability equations for IASEN-2 [18] are as follows: Probability equations for IAON are as follows: Figure 8 shows the bandwidth comparison of MALN, IASEN-2, and IAON for network size , 32, 64, and 128. Bandwidth of IAON is better than the other two MINs [15, 18].

##### 5.3. Routing Time (rt)

It is the time that a data packet takes from a source node to the given destination node. It is calculated by the following formula: where routing times of MALN [15], IASEN-2 [18], and IAON are as follows:

##### 5.4. Arrival Time (*β*)

Arrival time is the time that a source node takes in order to send a data packet to all given destinations. It is given by the following formula: Therefore, arrival time of MALN, IASEN-2, and IAON is as follows: Arrival time is also explained in Example 3.

*Example 3. *Suppose we have to calculate the arrival time of a data packet for the network shown in Figure 9.

In Figure 9, we have taken a single stage IN. In this figure, red node is source, green nodes are destinations, and rests of the nodes are SEs of the network. At present, data packet is going through a light blue SE of network and data path is shown by green dotted arrows. It is assumed that a data packet is taking 0.1 ms from a SE to another SE. Hence, = 0.1 ms, = 3, , ms, , , ms is the arrival time of a data packet.

##### 5.5. Total Arrival Time

Total arrival time is the time that all generated data packets take from a source to all given destinations. It is given by the following formula: If are 100 then total arrival time of Example 3 will be ms.

##### 5.6. Single Switch Fault Arrival Time

When single switch is faulty in every stage of the network then the arrival time of all the data packets from a source to all the destinations is given by the following formula: In Example 3, the network has only one stage therefore, and we assumed that the light blue SE in Figure 9 is faulty then , .

##### 5.7. Double Switch Fault Arrival Time ()

When double switch is faulty in every stage of the network then in this case the arrival time of a data packet from a source to all the destinations is given by the following formula: We know that MALN [15] and IASEN-2 [18] are not Double Switch Fault Tolerant Network. Therefore, we cannot calculate the double switch fault arrival time of these networks.

In Example 3, now we assumed that the light blue and yellow SEs in Figure 9 are faulty then

##### 5.8. Probability of Acceptance (PA)

How many requests are going to be accepted by the destination side which is sent by the source side in a transfer cycle? PA is the answer of this question. Actually, during the data transmission process some data packets get blocked due to switch failure, link failure, or any other reason. Therefore, the total number of generated data packets on a source node and total number of accepted data packets by a destination node in a transfer cycle will not be the same [13]. It can be given by the following definition.

*Definition 4. **“It is defined as ratio of bandwidth to the expected number of requests generated per transfer cycle [15–18]”.*

Formula for PA [15–17] is Now, PA of MALN, IASEN-2, and IAON is given by the following formulas:

##### 5.9. Throughput (TP)

Basically, it is the average number of data packets which are going to be accepted by all destinations in a transfer cycle [13]. We can define it as follows.

*Definition 5. **“Throughput means average number of cells delivered by a network per unit time [15–17].”*

Formula for TP is [13] Here, is the transmission time of a MIN in ms.

TP of MALN [15], IASEN-2 [18], and IAON is given by the following formulas:

##### 5.10. Processor Utilization (PU)

In each transfer cycle, data packets are transmitted from source side to destination side [13–16]. For this transmission, processor plays a vital role in order to make this computation fast and efficient. Therefore, a specific amount of time is taken by the processor for each transfer cycle [15]. This time is considered as the utilization time of the processor and can be defined as follows.

*Definition 6. **“PU is defined as percentage of time the processor is active doing computation without accessing the global memory [15–17].”*

Formula for PU [13] is PU of MALN [15], IASEN-2 [18], and IAON is given by the following formulas

##### 5.11. Processor Power (PP)

PP is calculated on the behalf of processors which are used during the transmission of data packets [13]. It can be defined as follows.

*Definition 7. **“PP is defined as sum of processor utilization over the number of processors [13, 17].”*

Formula for PP is PP of MALN [15], IASEN-2 [18], and IAON is given by the following formulas: Now, we have shown the results which were obtained using the above-mentioned formulas.

Figure 10 shows the probability of acceptance of MALN [15], IASEN-2 [18], and IAON in faulty and nonfaulty cases for network size , 32, 64, and 128. Both figures show that IAON is better than MALN and IASEN-2 in terms of PA.

Figure 11 shows the throughput of MALN [15], IASEN-2 [18], and IAON in faulty and nonfaulty cases for network size , 32, 64, and 128. This figure shows that IAON is better than MALN and IASEN-2 in terms of TP. In Figures 11, 12, 13, 14, and 15 we have shown the performance of MALN_S, IASEN-2_S, IAON_S, and IAON_D. The significance of these networks is as follows: MALN_S: MALN [15] is Single Switch Fault Tolerant in every stage, IASEN-2_S: IASEN-2 [18] is Single Switch Fault Tolerant in every stage, IAON_S: IAON is Single Switch Fault Tolerant in every stage, IAON_D: IAON is Double Switch Fault Tolerant in every stage.

Figures 12 and 13 show the processor utilization of MALN [15], IASEN-2 [18], and IAON in faulty and nonfaulty cases for network size , 32, 64, and 128. Both figures show that IAON is better than MALN and IASEN-2 in terms of PU.

Figures 14 and 15 show the processing power of MALN [15], IASEN-2 [18], and IAON in faulty and nonfaulty cases for network size , 32, 64, and 128. Both figures show that IAON is better than MALN and IASEN-2 in terms of PP.

In Figures 11, 12, 13, 14, and 15, the time is converted from ms to seconds to explain the results evidently.

#### 6. Conclusion

Faults are not a new issue in the MINs. However, developing a MIN with high performance and great fault tolerability is an important factor in recent networks. In this paper, we have proved that IAON can tolerate concurrently 2-faulty SEs in each stage. Also we have demonstrated that it has more alternate paths for data transmission as compared to MALN and IASEN-2. The routing algorithm of IAON is a generalized algorithm for message broadcasting and it provides the suitable way to all data packets to reach the given destinations in faulty and nonfaulty situations. Furthermore, all the performance factors such as probability of acceptance, throughput, processor utilization, and processing power of IAON are better than MALN and IASEN-2 in faulty and nonfaulty cases. In future, the interconnection pattern of IAON can be changed in such a way that it can produce better results in crucial faulty situations.

#### References

- K. Hwang,
*Advanced Computer Architecture: Parallelism, Scalability, Programmability*, Tata McGraw-Hill, Noida, India, 2000. - J. Duato, S. Yalamanchili, and L. M. Ni,
*Interconnection Networks: An Engineering Approach*, Morgan Kaufmann, 2003. - W. Dally and B. Towles,
*Principles and Practices of Interconnection Networks*, Morgan Kaufmann, San Francisco, Calif, USA, 2004. - C. C. Fan and J. Bruck, “Tolerating multiple faults in Multistage Interconnection Networks with minimal extra stages,”
*IEEE Transactions on Computers*, vol. 49, no. 9, pp. 998–1004, 2000. View at Publisher · View at Google Scholar · View at Scopus - J. Garofalakis and E. Stergiou, “An approximate analytical performance model for multistage interconnection networks with backpressure blocking mechanism,”
*Journal of Communications*, vol. 5, no. 3, pp. 247–261, 2010. View at Publisher · View at Google Scholar · View at Scopus - D. C. Vasiliadis, G. E. Rizos, S. V. Margariti, and L. E. Tsiantis, “Comparative Study of blocking mechanisms for Packet Switched Omega Networks,” in
*Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications*, pp. 18–22, Corfu Island, Greece, 2007. - V. P. Bhardwaj, Nitin, and V. Tyagi, “An algorithmic approach to minimize the conflicts in an optical multistage interconnection network,” in
*Advances in Computing and Communications*, vol. 191 of*Communications in Computer and Information Science Series (CCIS)*, pp. 568–576, Springer, 2011. View at Google Scholar - V. P. Bhardwaj and Nitin, “Applying address selection algorithm on nonblocking optical multi-stage interconnection network,” in
*Proceedings of the IEEE World Congress on Information and Communication Technologies*, pp. 694–698, Mumbai, India, 2011. - D. C. Vasiliadis, G. E. Rizos, and C. Vassilakisa, “Performance analysis of dual-priority multilayermultistage interconnection networks undermulticast environment,”
*Journal of Networks*, vol. 6, no. 6, pp. 858–871, 2011. View at Publisher · View at Google Scholar · View at Scopus - M. Choi, N. Park, and F. Lombardi, “Modeling and analysis of fault tolerant multistage interconnection networks,”
*IEEE Transactions on Instrumentation and Measurement*, vol. 52, no. 5, pp. 1509–1519, 2003. View at Publisher · View at Google Scholar · View at Scopus - D. Vasiliadis, G. Rizos, and C. Vassilakis, “Performance study of multilayered multistage interconnection networks under hotspot traffic conditions,”
*Journal of Computer Systems, Networks, and Communications*, vol. 2010, Article ID 403056, 11 pages, 2010. View at Publisher · View at Google Scholar · View at Scopus - D. C. Vasiliadis, G. E. Rizos, and C. Vassilakis, “Class-based weighted fair queuing scheduling on dual-priority delta networks,”
*Journal of Computer Networks and Communications*, vol. 2012, Article ID 859694, 13 pages, 2012. View at Publisher · View at Google Scholar - J. Sengupta,
*Interconnection Networks For Parallel Processing*, Deep & Deep Publications, 2005. - R. Mahajan and R. Vig, “Performance and reliability analysis of new fault-tolerant advance omega network,”
*WSEAS Transactions on Computers*, vol. 7, no. 8, pp. 1280–1290, 2008. View at Google Scholar · View at Scopus - A. Gupta and P. K. Bansal, “Fault tolerant irregular modified alpha network and evaluation of performance parameters,”
*International Journal of Computer Applications*, vol. 4, no. 1, pp. 9–13, 2010. View at Google Scholar - M. Ghai, V. Chopra, and K. K. Cheema, “Performance analysis of fault-tolerant irregular baseline multistage interconnection network,”
*International Journal on Computer Science and Engineering*, vol. 2, no. 9, pp. 3079–3084, 2010. View at Google Scholar - K. Kaur, P. Kaur, and H. Sadawarti, “Performance analysis of new irregular multistage interconnection network,”
*International Journal of Advanced Engineering Sciences and Technologies*, vol. 9, pp. 82–86, 2011. View at Google Scholar - V. P. Bhardwaj and Nitin, “A new fault tolerant routing algorithm for IASEN-2,” in
*Proceedings of the 2nd IEEE International Conference on Advances in Computing and Communications (ICACC '12)*, pp. 199–202, Kerala, India, 2012. - Nitin, “On asymptotic analysis of packet and wormhole switched routing algorithm for application-specific Networks-on-Chip,”
*Journal of Computer and Electrical Engineering*, vol. 2012, Article ID 216406, 27 pages, 2012. View at Publisher · View at Google Scholar - S. Mittal and Nitin, “Memory map: a multiprocessor cache simulator,”
*Journal of Electrical and Computer Engineering*, vol. 2012, Article ID 365091, 12 pages, 2012. View at Publisher · View at Google Scholar - Nitin, R. Vaish, and U. Shrivastava, “On a deadlock and performance analysis of ALBR and DAR algorithm on X-Torus topology by optimal utilization of Cross Links and minimal lookups,”
*Journal of Supercomputing*, vol. 59, no. 3, pp. 1252–1288, 2010. View at Publisher · View at Google Scholar · View at Scopus - Nitin and D. S. Chauhan, “Stochastic communication for application specific Networks-on-Chip,”
*Journal of Supercomputing*, vol. 59, no. 2, pp. 779–810, 2010. View at Publisher · View at Google Scholar - Nitin and D. S. Chauhan, “Comparative analysis of traffic patterns on k-ary n-tree using adaptive algorithms based on Burton normal form,”
*Journal of Supercomputing*, vol. 59, no. 2, pp. 569–588, 2010. View at Publisher · View at Google Scholar - Nitin, S. Garhwal, and N. Srivastava, “Designing a fault-tolerant fully-chained combining switches multi-stage interconnection network with disjoint paths,”
*Journal of Supercomputing*, vol. 55, no. 3, pp. 400–431, 2011. View at Publisher · View at Google Scholar · View at Scopus - Nitin and A. Subramanian, “Efficient algorithms and methods to solve dynamic MINs stability problem using stable matching with complete ties,”
*Journal of Discrete Algorithms*, vol. 6, no. 3, pp. 353–380, 2008. View at Publisher · View at Google Scholar · View at Scopus - D. Nitin, “Component Level reliability analysis of fault-tolerant hybrid MINs,”
*WSEAS Transactions on Computers*, vol. 5, no. 9, pp. 1851–1859, 2006. View at Google Scholar · View at Scopus - Nitin and D. S. Chauhan, “A new fault tolerant routing algorithm for MALN-2,” in
*Eco-friendly Computing and Communication Systems*, Communications in Computer and Information Science, pp. 247–254, Springer, 2012. View at Google Scholar - C. W. Chen and C. P. Chung, “Designing a disjoint paths interconnection network with fault tolerance and collision solving,”
*Journal of Supercomputing*, vol. 34, no. 1, pp. 63–80, 2005. View at Publisher · View at Google Scholar · View at Scopus - V.P. Bhardwaj and Nitin, “A new fault tolerant routing algorithm for advance irregular alpha multistage interconnection network,” in
*Advances in Computer Science, Engineering & Applications*, Advances in Intelligent and Soft Computing, pp. 979–987, Springer, 2012. View at Google Scholar - C. W. Chen, “Design schemes of dynamic rerouting networks with destination tag routing for tolerating faults and preventing collisions,”
*Journal of Supercomputing*, vol. 38, no. 3, pp. 307–326, 2006. View at Publisher · View at Google Scholar · View at Scopus - B. V. Suresh Kumar, M. Venkata Rao, and M. A. Ram Prasad, “Adaptive fault tolerant routing in interconnection networks: a review,”
*International Journal of Advanced Networking and Applications*, vol. 02, no. 06, pp. 933–940, 2011. View at Google Scholar - S. Murali, D. Atienza, L. Benini, and G. De Micheli, “A method for routing packets across multiple paths in NoCs with in-order delivery and fault-tolerance gaurantees,”
*VLSI Design*, vol. 2007, Article ID 37627, 11 pages, 2007. View at Publisher · View at Google Scholar · View at Scopus - Nitin and D. S. Chauhan, “A new fault-tolerant routing algorithm for IMABN-2,” in
*Proceedings of the 2nd IEEE International Conference on Advances in Computing and Communications (ICACC '12)*, pp. 215–218, Kerala, India, 2012. - V. P. Bhardwaj and Nitin, “A new fault tolerant routing algorithm for advance irregular augmented shuffle exchange network,” in
*Proceedings of the 14th IEEE International Conference on Computer Modeling and Simulation (UKSIM '12)*, pp. 505–509, Emmanuel College, Cambridge, UK, 2012.